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| author | Keith Hui <buurin@gmail.com> | 2017-09-02 17:59:41 -0400 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-09-12 08:07:25 +0000 |
| commit | f3ec5ed5559c59a63419f20246751e6f39225ef7 (patch) | |
| tree | d08b2430659ce75f27bd14f09d5d92197fcaceb2 /src/southbridge/amd | |
| parent | 0a9982f3fb7d20325b437656205f450505967a3d (diff) | |
| download | coreboot-f3ec5ed5559c59a63419f20246751e6f39225ef7.tar.xz | |
cpu/intel/slot_1: Increase CAR size to 8KiB
Because cpu/intel/car/romstage.c assumes a 8KiB stack size
when setting up stack guards, and all Slot 1 compatible
CPUs have enough L1 cache available for the increase.
Adjust DCACHE_RAM_BASE to match.
Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz
Tualeron. The latter actually requires this patch to boot
successfully.
Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/amd')
0 files changed, 0 insertions, 0 deletions