AMD/agesa: Add functions for AMD PCI IRQ routing

Port the changes that were made in amd/cimx to amd/agesa
as were done in:
   commit c93a75a5ab067f86104028b74d92fc54cb939cd5
   Author: Mike Loptien <mike.loptien@se-eng.com>
   Date:   Fri Jun 6 15:16:29 2014 -0600

      AMD/CIMx: Add functions for AMD PCI IRQ routing

This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.

Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

16 files changed, 818 insertions, 283 deletions

diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index e2f3f9c422..57128d9cac 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -16,3 +16,9 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += agesa
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += agesa
+
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
new file mode 100644
index 0000000000..01f769c46d
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_DEFS_H
+#define AMD_PCI_INT_DEFS_H
+
+/*
+ * PIRQ and device routing - these define the index
+ * into the FCH PCI_INTR 0xC00/0xC01 interrupt
+ * routing table
+ */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
+#define FCH_INT_TABLE_SIZE 0x54
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+#define FCH_INT_TABLE_SIZE 0x42
+#endif
+
+#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
+#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
+#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
+#define PIRQ_ASF	0x12	/* ASF */
+#define PIRQ_HDA	0x13	/* HDA		14h.2 */
+#define PIRQ_FC		0x14	/* FC */
+#define PIRQ_GEC	0x15	/* GEC */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+#define PIRQ_SD     0x17	/* SD */
+#endif
+#define PIRQ_IMC0	0x20	/* IMC INT0 */
+#define PIRQ_IMC1	0x21	/* IMC INT1 */
+#define PIRQ_IMC2	0x22	/* IMC INT2 */
+#define PIRQ_IMC3	0x23	/* IMC INT3 */
+#define PIRQ_IMC4	0x24	/* IMC INT4 */
+#define PIRQ_IMC5	0x25	/* IMC INT5 */
+#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
+#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
+#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
+#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
+#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
+#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
+#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
+#define PIRQ_IDE	0x40	/* IDE		14h.1 */
+#define PIRQ_SATA	0x41	/* SATA		11h.0 */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
+#define PIRQ_SD     0x42	/* SD		14h.7 */
+#define PIRQ_GPP0	0x50	/* GPP INT 0 */
+#define PIRQ_GPP1	0x51	/* GPP INT 1 */
+#define PIRQ_GPP2	0x52	/* GPP INT 2 */
+#define PIRQ_GPP3	0x53	/* GPP INT 3 */
+#endif
+
+#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
new file mode 100644
index 0000000000..75efd67192
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x40] = "IDE\t", "SATA\t",
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
+};
+#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB",
+	[0x40] = "RSVD\t", "SATA\t",
+};
+#endif
+
+#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c
index 58498f4ab6..e8836e4c7d 100644
--- a/src/southbridge/amd/agesa/hudson/pci.c
+++ b/src/southbridge/amd/agesa/hudson/pci.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,11 +24,35 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include "hudson.h"
+#include <southbridge/amd/amd_pci_util.h>
+#include <bootstate.h>
 
 static void pci_init(struct device *dev)
 {
 }
 
+/*
+ * Update the PCI devices with a valid IRQ number
+ * that is set in the mainboard PCI_IRQ structures.
+ */
+static void set_pci_irqs(void *unused)
+{
+	/* Write PCI_INTR regs 0xC00/0xC01 */
+	write_pci_int_table();
+
+	/* Write IRQs for all devicetree enabled devices */
+	write_pci_cfg_irqs();
+}
+
+/*
+ * Hook this function into the PCI state machine
+ * on entry into BS_DEV_ENABLE.
+ */
+BOOT_STATE_INIT_ENTRIES(pci_irq_update) = {
+	BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY,
+	                      set_pci_irqs, NULL),
+};
+
 static struct pci_operations lops_pci = {
 	.set_subsystem = 0,
 };
diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h
new file mode 100644
index 0000000000..b66a23258c
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/pci_devs.h
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _AGESA_HUDSON_PCI_DEVS_H_
+#define _AGESA_HUDSON_PCI_DEVS_H_
+
+#define BUS0 0
+
+/* XHCI */
+#define XHCI_DEV 0x10
+#define XHCI_FUNC 0
+#define XHCI_DEVID 0x7814
+#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
+
+/* SATA */
+#define SATA_DEV 0x11
+#define SATA_FUNC 0
+#define SATA_IDE_DEVID 0x7800
+#define AHCI_DEVID_MS 0x7801
+#define AHCI_DEVID_AMD 0x7804
+#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
+
+/* OHCI */
+#define OHCI1_DEV 0x12
+#define OHCI1_FUNC 0
+#define OHCI2_DEV 0x13
+#define OHCI2_FUNC 0
+#define OHCI3_DEV 0x16
+#define OHCI3_FUNC 0
+#define OHCI4_DEV 0x14
+#define OHCI4_FUNC 5
+#define OHCI_DEVID 0x7807
+#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
+#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
+#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
+#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
+
+/* EHCI */
+#define EHCI1_DEV 0x12
+#define EHCI1_FUNC 2
+#define EHCI2_DEV 0x13
+#define EHCI2_FUNC 2
+#define EHCI3_DEV 0x22
+#define EHCI3_FUNC 2
+#define EHCI_DEVID 0x7808
+#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
+#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
+#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
+
+/* SMBUS */
+#define SMBUS_DEV 0x14
+#define SMBUS_FUNC 0
+#define SMBUS_DEVID 0x780B
+#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
+
+/* IDE */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
+#define IDE_DEV 0x14
+#define IDE_FUNC 1
+# define IDE_DEVID 0x780C
+# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
+#endif
+
+/* HD Audio */
+#define HDA_DEV 0x14
+#define HDA_FUNC 2
+#define HDA_DEVID 0x780D
+#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
+
+/* LPC BUS */
+#define PCU_DEV 0x14
+#define LPC_FUNC 3
+#define LPC_DEVID 0x780E
+#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
+
+/* PCI Ports */
+#define SB_PCI_PORT_DEV 0x14
+#define SB_PCI_PORT_FUNC 4
+# define SB_PCI_PORT_DEVID 0x780F
+# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
+
+/* SD Controller */
+#define SD_DEV 0x14
+#define SD_FUNC 7
+#define SD_DEVID 0x7806
+#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
+
+/* PCIe Ports */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON)
+#define SB_PCIE_DEV 0x15
+#define SB_PCIE_PORT1_FUNC 0
+#define SB_PCIE_PORT2_FUNC 1
+#define SB_PCIE_PORT3_FUNC 2
+#define SB_PCIE_PORT4_FUNC 3
+#define SB_PCIE_PORT1_DEVID 0x7820
+#define SB_PCIE_PORT2_DEVID 0x7821
+#define SB_PCIE_PORT3_DEVID 0x7822
+#define SB_PCIE_PORT4_DEVID 0x7823
+#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
+#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
+#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
+#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
+#endif
+
+#endif /* _AGESA_HUDSON_PCI_DEVS_H_ */
diff --git a/src/southbridge/amd/amd_pci_util.c b/src/southbridge/amd/amd_pci_util.c
new file mode 100644
index 0000000000..9f2cc5c1ee
--- /dev/null
+++ b/src/southbridge/amd/amd_pci_util.c
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include "amd_pci_util.h"
+#include <pc80/i8259.h>
+#include "amd_pci_int_defs.h"
+#include "amd_pci_int_types.h"
+
+#ifndef __PRE_RAM__
+
+const struct pirq_struct * pirq_data_ptr = NULL;
+u32 pirq_data_size = 0;
+const u8 * intr_data_ptr = NULL;
+const u8 * picr_data_ptr = NULL;
+
+/*
+ * Read the FCH PCI_INTR registers 0xC00/0xC01 at a
+ * given index and a given PIC (0) or IOAPIC (1) mode
+ */
+u8 read_pci_int_idx(u8 index, int mode)
+{
+	outb((mode << 7) | index, PCI_INTR_INDEX);
+	return inb(PCI_INTR_DATA);
+}
+
+/*
+ * Write a value to the FCH PCI_INTR registers 0xC00/0xC01
+ * at a given index and PIC (0) or IOAPIC (1) mode
+ */
+void write_pci_int_idx(u8 index, int mode, u8 data)
+{
+	outb((mode << 7) | index, PCI_INTR_INDEX);
+	outb(data, PCI_INTR_DATA);
+}
+
+/*
+ * Write the FCH PCI_INTR registers 0xC00/0xC01 with values
+ * given in global variables intr_data and picr_data.
+ * These variables are defined in mainboard.c
+ */
+void write_pci_int_table (void)
+{
+	u8 byte;
+
+	if(picr_data_ptr == NULL || intr_data_ptr == NULL){
+		printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
+				"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
+		return;
+	}
+
+	/* PIC IRQ routine */
+	printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n"
+			"\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n");
+	for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) {
+		if (intr_types[byte]) {
+			write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]);
+			printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n",
+					byte, intr_types[byte], read_pci_int_idx(byte, 0));
+		}
+	}
+
+	/* APIC IRQ routine */
+	printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n"
+			"\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n");
+	for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) {
+		if (intr_types[byte]) {
+			write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]);
+			printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n",
+					byte, intr_types[byte], read_pci_int_idx(byte, 1));
+		}
+	}
+}
+
+/*
+ * Function to write the PCI config space Interrupt
+ * registers based on the values given in PCI_INTR
+ * table at I/O port 0xC00/0xC01
+ */
+void write_pci_cfg_irqs(void)
+{
+	device_t dev = NULL;		/* Our current device to route IRQs to */
+	device_t target_dev = NULL;	/* The bridge that a device may be connected to */
+	u16 int_pin = 0;	/* Value of the INT_PIN register 0x3D */
+	u16 target_pin = 0;	/* Pin we will search our tables for */
+	u16 int_line = 0;	/* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */
+	u16 pci_intr_idx = 0;	/* Index into PCI_INTR table, 0xC00/0xC01 */
+	u8  bus = 0;		/* A PCI Device Bus number */
+	u16 devfn = 0;		/* A PCI Device and Function number */
+	u8  bridged_device = 0;	/* This device is on a PCI bridge */
+	u32 i = 0;
+
+	if (pirq_data_ptr == NULL) {
+		printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
+				" 'mainboard_pirq_data' structure does not exist\n");
+		return;
+	}
+
+	/* Populate the PCI cfg space header with the IRQ assignment */
+	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
+
+	for (dev = all_devices; dev; dev = dev->next) {
+		/*
+		 * Step 1: Get the INT_PIN and device structure to look for in the
+		 * PCI_INTR table pirq_data
+		 */
+		target_dev = NULL;
+		target_pin = get_pci_irq_pins(dev, &target_dev);
+		if (target_dev == NULL)
+			continue;
+
+		if (target_pin < 1)
+			continue;
+
+		/* Get the original INT_PIN for record keeping */
+		int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+		if (int_pin < 1 || int_pin > 4)
+			continue;	/* Device has invalid INT_PIN so skip it */
+
+		bus   = target_dev->bus->secondary;
+		devfn = target_dev->path.pci.devfn;
+
+		/*
+		 * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR
+		 * register (0xC00) index for this device
+		 */
+		pci_intr_idx = 0xBAD;	/* Will check to make sure it changed */
+		for (i = 0; i < pirq_data_size; i++) {
+			if (pirq_data_ptr[i].devfn != devfn)
+				continue;
+
+			/* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */
+			pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1];
+			printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i);
+			break;
+		}
+
+		/*
+		 * Step 3: Make sure we got a valid index and use it to get
+		 * the IRQ number from the PCI_INTR register table
+		 */
+		if (pci_intr_idx == 0xBAD) {	/* Not on a bridge or in pirq_data table, skip it */
+			printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn);
+			continue;
+		} else if (pci_intr_idx == 0x1F) {	/* Index found is not defined */
+			printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n");
+			continue;
+		} else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) {	/* Index out of bounds */
+			printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n",
+					__func__, pci_intr_idx, FCH_INT_TABLE_SIZE);
+			continue;
+		}
+
+		/* Find the value to program into the INT_LINE register from the PCI_INTR registers */
+		int_line = read_pci_int_idx(pci_intr_idx, 0);
+		if (int_line == PIRQ_NC) {	/* The IRQ found is disabled */
+			printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n");
+			continue;
+		}
+
+		/*
+		 * Step 4: Program the INT_LINE register in this device's
+		 * PCI config space with the IRQ number we found in step 3
+		 * and make it Level Triggered
+		 */
+		pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line);
+
+		/* Set this IRQ to level triggered since it is used by a PCI device */
+		i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
+
+		/*
+		 * Step 5: Print out debug info and move on to next device
+		 */
+		printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n",
+						int_pin, pin_to_str(int_pin));
+		if (bridged_device)
+			printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
+							target_pin, pin_to_str(target_pin));
+		printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n"
+						"\tINT_LINE\t: 0x%X (IRQ %d)\n",
+						pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line);
+	}	/* for (dev = all_devices) */
+	printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
+}
+#endif /* __PRE_RAM__ */
diff --git a/src/southbridge/amd/amd_pci_util.h b/src/southbridge/amd/amd_pci_util.h
new file mode 100644
index 0000000000..1d1e52baaf
--- /dev/null
+++ b/src/southbridge/amd/amd_pci_util.h
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_UTIL_H
+#define AMD_PCI_UTIL_H
+
+#include <stdint.h>
+#include "amd_pci_int_defs.h"
+
+/* FCH index/data registers */
+#define PCI_INTR_INDEX	0xc00
+#define PCI_INTR_DATA	0xc01
+
+#ifndef __PRE_RAM__
+
+struct pirq_struct {
+	u8 devfn;
+	u8 PIN[4];	/* PINA/B/C/D are index 0/1/2/3 */
+};
+
+extern const struct pirq_struct * pirq_data_ptr;
+extern u32 pirq_data_size;
+extern const u8 * intr_data_ptr;
+extern const u8 * picr_data_ptr;
+
+u8 read_pci_int_idx(u8 index, int mode);
+void write_pci_int_idx(u8 index, int mode, u8 data);
+void write_pci_cfg_irqs(void);
+void write_pci_int_table (void);
+#endif /* __PRE_RAM */
+
+#endif /* AMD_PCI_UTIL_H */
diff --git a/src/southbridge/amd/cimx/cimx_util.c b/src/southbridge/amd/cimx/cimx_util.c
index 5d9276f78b..7909b68df9 100644
--- a/src/southbridge/amd/cimx/cimx_util.c
+++ b/src/southbridge/amd/cimx/cimx_util.c
@@ -21,204 +21,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <arch/io.h>
-#include <string.h>
 #include "cimx_util.h"
-#include <pc80/i8259.h>
-
-#ifndef __PRE_RAM__
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) || \
-	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900)
-const char * intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700)
-const char * intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t",
-	[0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t",
-	[0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-};
-#endif
-
-const struct pirq_struct * pirq_data_ptr = NULL;
-u32 pirq_data_size = 0;
-const u8 * intr_data_ptr = NULL;
-const u8 * picr_data_ptr = NULL;
-
-/*
- * Read the FCH PCI_INTR registers 0xC00/0xC01 at a
- * given index and a given PIC (0) or IOAPIC (1) mode
- */
-u8 read_pci_int_idx(u8 index, int mode)
-{
-	outb((mode << 7) | index, PCI_INTR_INDEX);
-	return inb(PCI_INTR_DATA);
-}
-
-/*
- * Write a value to the FCH PCI_INTR registers 0xC00/0xC01
- * at a given index and PIC (0) or IOAPIC (1) mode
- */
-void write_pci_int_idx(u8 index, int mode, u8 data)
-{
-	outb((mode << 7) | index, PCI_INTR_INDEX);
-	outb(data, PCI_INTR_DATA);
-}
-
-/*
- * Write the FCH PCI_INTR registers 0xC00/0xC01 with values
- * given in global variables intr_data and picr_data.
- * These variables are defined in mainboard.c
- */
-void write_pci_int_table (void)
-{
-	u8 byte;
-
-	if(picr_data_ptr == NULL || intr_data_ptr == NULL){
-		printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
-				"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
-		return;
-	}
-
-	/* PIC IRQ routine */
-	printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for PIC mode PCI IRQ routing:\n"
-			"\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n");
-	for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) {
-		if (intr_types[byte]) {
-			write_pci_int_idx(byte, 0, (u8) picr_data_ptr[byte]);
-			printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n",
-					byte, intr_types[byte], read_pci_int_idx(byte, 0));
-		}
-	}
-
-	/* APIC IRQ routine */
-	printk(BIOS_DEBUG, "PCI_INTR tables: Writing registers C00/C01 for APIC mode PCI IRQ routing:\n"
-			"\tPCI_INTR_INDEX\t\tPCI_INTR_DATA\n");
-	for (byte = 0; byte < FCH_INT_TABLE_SIZE; byte++) {
-		if (intr_types[byte]) {
-			write_pci_int_idx(byte, 1, (u8) intr_data_ptr[byte]);
-			printk(BIOS_DEBUG, "\t0x%02X %s\t: 0x%02X\n",
-					byte, intr_types[byte], read_pci_int_idx(byte, 1));
-		}
-	}
-}
-
-/*
- * Function to write the PCI config space Interrupt
- * registers based on the values given in PCI_INTR
- * table at I/O port 0xC00/0xC01
- */
-void write_pci_cfg_irqs(void)
-{
-	device_t dev = NULL;		/* Our current device to route IRQs to */
-	device_t target_dev = NULL;	/* The bridge that a device may be connected to */
-	u16 int_pin = 0;	/* Value of the INT_PIN register 0x3D */
-	u16 target_pin = 0;	/* Pin we will search our tables for */
-	u16 int_line = 0;	/* IRQ number read from PCI_INTR table and programmed to INT_LINE reg 0x3C */
-	u16 pci_intr_idx = 0;	/* Index into PCI_INTR table, 0xC00/0xC01 */
-	u8  bus = 0;		/* A PCI Device Bus number */
-	u16 devfn = 0;		/* A PCI Device and Function number */
-	u8  bridged_device = 0;	/* This device is on a PCI bridge */
-	u32 i = 0;
-
-	if (pirq_data_ptr == NULL) {
-		printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because"
-				" 'mainboard_pirq_data' structure does not exist\n");
-		return;
-	}
-
-	/* Populate the PCI cfg space header with the IRQ assignment */
-	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
-
-	for (dev = all_devices; dev; dev = dev->next) {
-		/*
-		 * Step 1: Get the INT_PIN and device structure to look for in the
-		 * PCI_INTR table pirq_data
-		 */
-		target_dev = NULL;
-		target_pin = get_pci_irq_pins(dev, &target_dev);
-		if (target_dev == NULL)
-			continue;
-
-		if (target_pin < 1)
-			continue;
-
-		/* Get the original INT_PIN for record keeping */
-		int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN);
-		if (int_pin < 1 || int_pin > 4)
-			continue;	/* Device has invalid INT_PIN so skip it */
-
-		bus   = target_dev->bus->secondary;
-		devfn = target_dev->path.pci.devfn;
-
-		/*
-		 * Step 2: Use the INT_PIN and DevFn number to find the PCI_INTR
-		 * register (0xC00) index for this device
-		 */
-		pci_intr_idx = 0xBAD;	/* Will check to make sure it changed */
-		for (i = 0; i < pirq_data_size; i++) {
-			if (pirq_data_ptr[i].devfn != devfn)
-				continue;
-
-			/* PIN_A is index 0 in pirq_data array but 1 in PCI cfg reg */
-			pci_intr_idx = pirq_data_ptr[i].PIN[target_pin - 1];
-			printk(BIOS_SPEW, "\tFound this device in pirq_data table entry %d\n", i);
-			break;
-		}
-
-		/*
-		 * Step 3: Make sure we got a valid index and use it to get
-		 * the IRQ number from the PCI_INTR register table
-		 */
-		if (pci_intr_idx == 0xBAD) {	/* Not on a bridge or in pirq_data table, skip it */
-			printk(BIOS_SPEW, "PCI Devfn (0x%x) not found in pirq_data table\n", devfn);
-			continue;
-		} else if (pci_intr_idx == 0x1F) {	/* Index found is not defined */
-			printk(BIOS_SPEW, "Got index 0x1F (Not Connected), perhaps this device was defined wrong?\n");
-			continue;
-		} else if (pci_intr_idx >= FCH_INT_TABLE_SIZE) {	/* Index out of bounds */
-			printk(BIOS_ERR, "%s: got 0xC00/0xC01 table index 0x%x, max is 0x%x\n",
-					__func__, pci_intr_idx, FCH_INT_TABLE_SIZE);
-			continue;
-		}
-
-		/* Find the value to program into the INT_LINE register from the PCI_INTR registers */
-		int_line = read_pci_int_idx(pci_intr_idx, 0);
-		if (int_line == PIRQ_NC) {	/* The IRQ found is disabled */
-			printk(BIOS_SPEW, "Got IRQ 0x1F (disabled), perhaps this device was defined wrong?\n");
-			continue;
-		}
-
-		/*
-		 * Step 4: Program the INT_LINE register in this device's
-		 * PCI config space with the IRQ number we found in step 3
-		 * and make it Level Triggered
-		 */
-		pci_write_config8(dev, PCI_INTERRUPT_LINE, int_line);
-
-		/* Set this IRQ to level triggered since it is used by a PCI device */
-		i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
-
-		/*
-		 * Step 5: Print out debug info and move on to next device
-		 */
-		printk(BIOS_SPEW, "\tOrig INT_PIN\t: %d (%s)\n",
-						int_pin, pin_to_str(int_pin));
-		if (bridged_device)
-			printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
-							target_pin, pin_to_str(target_pin));
-		printk(BIOS_SPEW, "\tPCI_INTR idx\t: 0x%02x (%s)\n"
-						"\tINT_LINE\t: 0x%X (IRQ %d)\n",
-						pci_intr_idx, intr_types[pci_intr_idx], int_line, int_line);
-	}	/* for (dev = all_devices) */
-	printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
-}
-#endif /* __PRE_RAM__ */
 
 static void pmio_write_index(u16 port_base, u8 reg, u8 value)
 {
diff --git a/src/southbridge/amd/cimx/cimx_util.h b/src/southbridge/amd/cimx/cimx_util.h
index 841325143f..a16091aabd 100644
--- a/src/southbridge/amd/cimx/cimx_util.h
+++ b/src/southbridge/amd/cimx/cimx_util.h
@@ -23,73 +23,6 @@
 
 #include <stdint.h>
 
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) || \
-	IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900)
-#define FCH_INT_TABLE_SIZE 0x54
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
-#define PIRQ_ASF	0x12	/* ASF */
-#define PIRQ_HDA	0x13	/* HDA		14h.2 */
-#define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
-#define PIRQ_SATA	0x41	/* SATA		11h.0 */
-#define PIRQ_GPP0	0x50	/* GPP INT 0 */
-#define PIRQ_GPP1	0x51	/* GPP INT 1 */
-#define PIRQ_GPP2	0x52	/* GPP INT 2 */
-#define PIRQ_GPP3	0x53	/* GPP INT 3 */
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700)
-#define FCH_INT_TABLE_SIZE 0xD
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_ACPI	0x04	/* ACPI */
-#define PIRQ_SMBUS	0x05	/* SMBUS */
-/* Index 6, 7, 8 are all reserved */
-#define PIRQ_E		0x09	/* INT E */
-#define PIRQ_F		0x0A	/* INT F */
-#define PIRQ_G		0x0B	/* INT G */
-#define PIRQ_H		0x0C	/* INT H */
-#endif
-
 /* FCH index/data registers */
 #define BIOSRAM_INDEX	0xcd4
 #define BIOSRAM_DATA	0xcd5
@@ -105,22 +38,4 @@ u8 pm_ioread(u8 reg);
 void pm2_iowrite(u8 reg, u8 value);
 u8 pm2_ioread(u8 reg);
 
-#ifndef __PRE_RAM__
-
-struct pirq_struct {
-u8 devfn;
-u8 PIN[4];	/* PINA/B/C/D are index 0/1/2/3 */
-};
-
-extern const struct pirq_struct * pirq_data_ptr;
-extern u32 pirq_data_size;
-extern const u8 * intr_data_ptr;
-extern const u8 * picr_data_ptr;
-
-u8 read_pci_int_idx(u8 index, int mode);
-void write_pci_int_idx(u8 index, int mode, u8 data);
-void write_pci_cfg_irqs(void);
-void write_pci_int_table (void);
-#endif /* __PRE_RAM */
-
 #endif /* CIMX_UTIL_H */
diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h
new file mode 100644
index 0000000000..fb1cb9d12d
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_DEFS_H
+#define AMD_PCI_INT_DEFS_H
+
+/*
+ * PIRQ and device routing - these define the index
+ * into the FCH PCI_INTR 0xC00/0xC01 interrupt
+ * routing table
+ */
+#define FCH_INT_TABLE_SIZE 0xD
+#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_ACPI	0x04	/* ACPI */
+#define PIRQ_SMBUS	0x05	/* SMBUS */
+/* Index 6, 7, 8 are all reserved */
+#define PIRQ_E		0x09	/* INT E */
+#define PIRQ_F		0x0A	/* INT F */
+#define PIRQ_G		0x0B	/* INT G */
+#define PIRQ_H		0x0C	/* INT H */
+
+#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h
new file mode 100644
index 0000000000..6c28e31913
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t",
+	[0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t",
+	[0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+};
+
+#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
new file mode 100644
index 0000000000..6f1ae8f005
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_DEFS_H
+#define AMD_PCI_INT_DEFS_H
+
+/*
+ * PIRQ and device routing - these define the index
+ * into the FCH PCI_INTR 0xC00/0xC01 interrupt
+ * routing table
+ */
+#define FCH_INT_TABLE_SIZE 0x54
+
+#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
+#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
+#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
+#define PIRQ_ASF	0x12	/* ASF */
+#define PIRQ_HDA	0x13	/* HDA		14h.2 */
+#define PIRQ_FC		0x14	/* FC */
+#define PIRQ_GEC	0x15	/* GEC */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+#define PIRQ_IMC0	0x20	/* IMC INT0 */
+#define PIRQ_IMC1	0x21	/* IMC INT1 */
+#define PIRQ_IMC2	0x22	/* IMC INT2 */
+#define PIRQ_IMC3	0x23	/* IMC INT3 */
+#define PIRQ_IMC4	0x24	/* IMC INT4 */
+#define PIRQ_IMC5	0x25	/* IMC INT5 */
+#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
+#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
+#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
+#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
+#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
+#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
+#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
+#define PIRQ_IDE	0x40	/* IDE		14h.1 */
+#define PIRQ_SATA	0x41	/* SATA		11h.0 */
+#define PIRQ_GPP0	0x50	/* GPP INT 0 */
+#define PIRQ_GPP1	0x51	/* GPP INT 1 */
+#define PIRQ_GPP2	0x52	/* GPP INT 2 */
+#define PIRQ_GPP3	0x53	/* GPP INT 3 */
+
+#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
new file mode 100644
index 0000000000..173059c247
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x40] = "IDE\t", "SATA\t",
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
+};
+
+#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 8000601930..b132bf17d0 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -38,7 +38,7 @@
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
 #include "smbus.h"
 #include "fan.h"
-#include <southbridge/amd/cimx/cimx_util.h>
+#include <southbridge/amd/amd_pci_util.h>
 
 /*implement in mainboard.c*/
 void set_pcie_reset(void);
diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h
new file mode 100644
index 0000000000..6f1ae8f005
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_DEFS_H
+#define AMD_PCI_INT_DEFS_H
+
+/*
+ * PIRQ and device routing - these define the index
+ * into the FCH PCI_INTR 0xC00/0xC01 interrupt
+ * routing table
+ */
+#define FCH_INT_TABLE_SIZE 0x54
+
+#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
+#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
+#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
+#define PIRQ_ASF	0x12	/* ASF */
+#define PIRQ_HDA	0x13	/* HDA		14h.2 */
+#define PIRQ_FC		0x14	/* FC */
+#define PIRQ_GEC	0x15	/* GEC */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+#define PIRQ_IMC0	0x20	/* IMC INT0 */
+#define PIRQ_IMC1	0x21	/* IMC INT1 */
+#define PIRQ_IMC2	0x22	/* IMC INT2 */
+#define PIRQ_IMC3	0x23	/* IMC INT3 */
+#define PIRQ_IMC4	0x24	/* IMC INT4 */
+#define PIRQ_IMC5	0x25	/* IMC INT5 */
+#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
+#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
+#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
+#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
+#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
+#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
+#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
+#define PIRQ_IDE	0x40	/* IDE		14h.1 */
+#define PIRQ_SATA	0x41	/* SATA		11h.0 */
+#define PIRQ_GPP0	0x50	/* GPP INT 0 */
+#define PIRQ_GPP1	0x51	/* GPP INT 1 */
+#define PIRQ_GPP2	0x52	/* GPP INT 2 */
+#define PIRQ_GPP3	0x53	/* GPP INT 3 */
+
+#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
new file mode 100644
index 0000000000..173059c247
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x40] = "IDE\t", "SATA\t",
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
+};
+
+#endif /* AMD_PCI_INT_TYPES_H */