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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-19 08:41:50 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-20 12:47:44 +0000
commit5be75d5311695316f0d34448b98299cbe8b91ea5 (patch)
tree4c51d81915c6575fc169ac51635f4875d212ed4e /src/southbridge/amd
parent830e0de40187183c34a1f558d83b65068b649e2a (diff)
downloadcoreboot-5be75d5311695316f0d34448b98299cbe8b91ea5.tar.xz
AGESA,binaryPI: Replace use of __PRE_RAM__
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/agesa/hudson/hudson.h7
-rw-r--r--src/southbridge/amd/agesa/hudson/imc.c2
-rw-r--r--src/southbridge/amd/cimx/sb800/fan.h4
-rw-r--r--src/southbridge/amd/cimx/sb900/cfg.c6
-rw-r--r--src/southbridge/amd/common/amd_pci_util.c3
-rw-r--r--src/southbridge/amd/common/amd_pci_util.h3
-rw-r--r--src/southbridge/amd/pi/hudson/hudson.h9
-rw-r--r--src/southbridge/amd/pi/hudson/imc.c2
8 files changed, 4 insertions, 32 deletions
diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h
index 5d9d8494c6..21a2129a5c 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.h
+++ b/src/southbridge/amd/agesa/hudson/hudson.h
@@ -61,14 +61,11 @@ static inline int hudson_ide_enable(void)
return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
}
-#ifndef __SMM__
-
void pm_write8(u8 reg, u8 value);
u8 pm_read8(u8 reg);
void pm_write16(u8 reg, u16 value);
u16 pm_read16(u16 reg);
-#ifdef __SIMPLE_DEVICE__
void hudson_lpc_port80(void);
void hudson_pci_port80(void);
void hudson_clk_output_48Mhz(void);
@@ -76,10 +73,6 @@ void hudson_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#else
void hudson_enable(struct device *dev);
-#endif /* __PRE_RAM__ */
-#endif /* __SMM__ */
-
#endif /* HUDSON_H */
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index 9ba07316e8..1d63c1e36a 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -54,7 +54,6 @@ void imc_reg_init(void)
#endif
}
-#ifndef __PRE_RAM__
void enable_imc_thermal_zone(void)
{
AMD_CONFIG_PARAMS StdHeader;
@@ -83,4 +82,3 @@ void enable_imc_thermal_zone(void)
WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number
WaitForEcLDN9MailboxCmdAck(&StdHeader);
}
-#endif
diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h
index f31e48645e..3734da10a0 100644
--- a/src/southbridge/amd/cimx/sb800/fan.h
+++ b/src/southbridge/amd/cimx/sb800/fan.h
@@ -16,10 +16,10 @@
#ifndef _SB800_FAN_H_
#define _SB800_FAN_H_
-#ifndef __PRE_RAM__
+#include <device/device.h>
+
void init_sb800_IMC_fans(struct device *dev);
void init_sb800_MANUAL_fans(struct device *dev);
-#endif
/* Fan Register Definitions */
#define FAN_0_OFFSET 0x00
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index 353d5771e0..2e4173fb92 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -243,15 +243,13 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
sb_config->PciClks = SB_PCI_CLOCK_RESERVED;
sb_config->hwm.hwmEnable = 0x0;
-#ifndef __PRE_RAM__
/* ramstage cimx config here */
- if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+ if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
}
//sb_config->
-#endif //!__PRE_RAM__
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
}
void SbPowerOnInit_Config(AMDSBCFG *sb_config)
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index f10a459bfd..b6d6308710 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -22,8 +22,6 @@
#include "amd_pci_int_defs.h"
#include "amd_pci_int_types.h"
-#ifndef __PRE_RAM__
-
const struct pirq_struct * pirq_data_ptr = NULL;
u32 pirq_data_size = 0;
const u8 *intr_data_ptr = NULL;
@@ -195,4 +193,3 @@ void write_pci_cfg_irqs(void)
} /* for (dev = all_devices) */
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
}
-#endif /* __PRE_RAM__ */
diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h
index 9a4695e29a..0a3ce23a84 100644
--- a/src/southbridge/amd/common/amd_pci_util.h
+++ b/src/southbridge/amd/common/amd_pci_util.h
@@ -23,8 +23,6 @@
#define PCI_INTR_INDEX 0xc00
#define PCI_INTR_DATA 0xc01
-#ifndef __PRE_RAM__
-
struct pirq_struct {
u8 devfn;
u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */
@@ -39,6 +37,5 @@ u8 read_pci_int_idx(u8 index, int mode);
void write_pci_int_idx(u8 index, int mode, u8 data);
void write_pci_cfg_irqs(void);
void write_pci_int_table (void);
-#endif /* __PRE_RAM */
#endif /* AMD_PCI_UTIL_H */
diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index 99e372158d..9511a6ad24 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -169,14 +169,11 @@ static inline int hudson_ide_enable(void)
return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
}
-#ifndef __SMM__
-
void pm_write8(u8 reg, u8 value);
u8 pm_read8(u8 reg);
void pm_write16(u8 reg, u16 value);
u16 pm_read16(u16 reg);
-#ifdef __PRE_RAM__
void hudson_lpc_port80(void);
void hudson_lpc_decode(void);
void hudson_pci_port80(void);
@@ -190,15 +187,9 @@ void lpc_wideio_16_window(uint16_t base);
void hudson_tpm_decode_spi(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#if CONFIG(HUDSON_UART)
void configure_hudson_uart(void);
-#endif
-#else
void hudson_enable(struct device *dev);
void s3_resume_init_data(void *FchParams);
-#endif /* __PRE_RAM__ */
-#endif /* __SMM__ */
-
#endif /* HUDSON_H */
diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c
index 9ea8172af5..6a01a764cb 100644
--- a/src/southbridge/amd/pi/hudson/imc.c
+++ b/src/southbridge/amd/pi/hudson/imc.c
@@ -51,7 +51,6 @@ void imc_reg_init(void)
pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8);
}
-#ifndef __PRE_RAM__
void enable_imc_thermal_zone(void)
{
AMD_CONFIG_PARAMS StdHeader;
@@ -80,4 +79,3 @@ void enable_imc_thermal_zone(void)
WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader);
WaitForEcLDN9MailboxCmdAck(&StdHeader);
}
-#endif