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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2019-01-15 11:15:23 +0100 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2019-01-16 07:13:39 +0000 |
| commit | 65ca24c02e0e9738781d4ca4d0cb3397cf9c2328 (patch) | |
| tree | f5079a5c731f3639ad0b1c71092070ba8fa6177f /src/southbridge/amd | |
| parent | d13b2d05085486bd077ac6f1d4a513345594b557 (diff) | |
| download | coreboot-65ca24c02e0e9738781d4ca4d0cb3397cf9c2328.tar.xz | |
siemens/mc_apl4: Change UART_FOR_CONSOLE index
This mainboard uses SOC internal UART 1 instead of UART 2 like all other
mc_apl1 mainboards.
Change-Id: Ib986962ed068fee019ffcec0391d43d5ab178458
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
0 files changed, 0 insertions, 0 deletions