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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-14 17:48:20 +0300 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-14 18:54:57 +0200 |
| commit | 04372975bd2d5c1ac94c6358a32cfdcafccc26e3 (patch) | |
| tree | ee24360c7b47519f8dd73f7edb0d4c1261c46e48 /src/southbridge/amd | |
| parent | 00cc7f4355ca1bdd621d4618f24f3336b29463cb (diff) | |
| download | coreboot-04372975bd2d5c1ac94c6358a32cfdcafccc26e3.tar.xz | |
AMD sb800 agesa/hudson: Use PCI defines
The original lines had contradicting comment and code.
This change follows the code and sets MASTER bit too.
Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3466
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/sb800/enable_usbdebug.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index c74ac9ac61..128885a525 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -50,6 +50,7 @@ void enable_usbdebug(unsigned int port) pci_write_config32(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, HUDSON_DEVN_BASE + 0x12, 2), + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); set_debug_port(port); } diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index f085eabecb..28a1665647 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -50,6 +50,7 @@ void enable_usbdebug(unsigned int port) pci_write_config32(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), EHCI_BAR_INDEX, CONFIG_EHCI_BAR); - pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), 0x04, 0x6); /* mem space enabe */ + pci_write_config8(PCI_DEV(0, SB800_DEVN_BASE + 0x12, 2), + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); set_debug_port(port); } |