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| author | Rudolf Marek <r.marek@asssembler.cz> | 2011-02-26 13:34:01 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2011-02-26 13:34:01 +0000 |
| commit | 199c694f49e2ecbc3bd2cc6c5e7d7570a4c3cf62 (patch) | |
| tree | 62e74168ba730c474889c0b14088a28a1632cb4d /src/southbridge/amd | |
| parent | ed1d116e62b57b9c5c8746d17ecbf842845d4be2 (diff) | |
| download | coreboot-199c694f49e2ecbc3bd2cc6c5e7d7570a4c3cf62.tar.xz | |
It adds support for automatic PSS object generation for AMD pre fam Fh CPU. Those CPUs require a hardcoded table, which I managed to rewrite during one particularly boring flight. Too pity it is only for Opteron CPUs. Someone needs to finish the second PDF for All others Athlons and Semprons.
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb700/early_setup.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 552086a7eb..383b24f577 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -232,6 +232,12 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn) pmio_write(0x42, byte); pmio_write(0x89, 0x10); + + /* Toggle the LDT_STOP# during FID/VID Change, this bit is documented + only in SB600! + While here, enable C states too + */ + pmio_write(0x67, 0x6); } void hard_reset(void) |