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| author | Jonathan A. Kollasch <jakllsch@kollasch.net> | 2012-01-07 10:17:50 -0600 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-01-08 20:43:02 +0100 |
| commit | b5d81eb43db54bd807af68744ebefa429c95843a (patch) | |
| tree | b3a00a7eb8bf2105ebf63907ca3b75cf5ae6f1b0 /src/southbridge/amd | |
| parent | f61fff92e4ff0de9c7e0efc6a8afaa42c5143822 (diff) | |
| download | coreboot-b5d81eb43db54bd807af68744ebefa429c95843a.tar.xz | |
rs780: correct comment in switching_gpp_configurations()
Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/rs780/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c index be80ed3e0e..527a710cfb 100644 --- a/src/southbridge/amd/rs780/pcie.c +++ b/src/southbridge/amd/rs780/pcie.c @@ -191,7 +191,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) reg = nbmisc_read_index(nb_dev, 0x22); reg |= 1 << 14; nbmisc_write_index(nb_dev, 0x22, reg); - /* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */ + /* 5.6.2.2. sets desired GPP configurations, bit7-10 */ reg = nbmisc_read_index(nb_dev, 0x2D); reg &= ~(0xF << 7); /* clean */ reg |= cfg->gpp_configuration << 7; |