x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

32 files changed, 118 insertions, 111 deletions

diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
index 258267ed04..5463d2bb90 100644
--- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 
 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	u32 base_regs = pci_ehci_base_regs(dev);
+	u8 *base_regs = pci_ehci_base_regs(dev);
 	u32 reg32;
 
 	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
@@ -48,7 +48,7 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 	reg32 &= ~(0xf << 28);
 	reg32 |= (port << 28);
 	reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */
-	write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
+	write32(base_regs + (DEBUGPORT_MISC_CONTROL / sizeof(u32)), reg32);
 }
 
 
diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c
index fd2c268a23..4ddfea2b8e 100644
--- a/src/southbridge/amd/agesa/hudson/hudson.c
+++ b/src/southbridge/amd/agesa/hudson/hudson.c
@@ -40,22 +40,22 @@
 
 void pm_write8(u8 reg, u8 value)
 {
-	write8(PM_MMIO_BASE + reg, value);
+	write8((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u8 pm_read8(u8 reg)
 {
-	return read8(PM_MMIO_BASE + reg);
+	return read8((void *)(PM_MMIO_BASE + reg));
 }
 
 void pm_write16(u8 reg, u16 value)
 {
-	write16(PM_MMIO_BASE + reg, value);
+	write16((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u16 pm_read16(u16 reg)
 {
-	return read16(PM_MMIO_BASE + reg);
+	return read16((void *)(PM_MMIO_BASE + reg));
 }
 
 #define PM_REG_USB_ENABLE	0xef
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
index d706292ab7..65b31fd828 100644
--- a/src/southbridge/amd/agesa/hudson/imc.c
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -27,22 +27,24 @@
 #include <Proc/Fch/Common/FchCommonCfg.h>
 #include <Proc/Fch/FchPlatform.h>
 
+#define VACPI_MMIO_VBASE ((u8 *)ACPI_MMIO_BASE)
+
 void imc_reg_init(void)
 {
 	/* Init Power Management Block 2 (PM2) Registers.
 	 * Check BKDG for AMD Family 16h for details. */
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x00, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x01, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x02, 0xf7);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x03, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x04, 0xff);
 
 #if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
-	write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x10, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x11, 0x06);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x12, 0xf7);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x13, 0xff);
+	write8(VACPI_MMIO_VBASE + PMIO2_BASE + 0x14, 0xff);
 #endif
 
 #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index d6ca215a6a..bc6564d1ec 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -82,7 +82,7 @@
 
 static void sm_init(device_t dev)
 {
-	setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 }
 
 static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h
index 53da00adfa..520c65fe51 100644
--- a/src/southbridge/amd/agesa/hudson/smi.h
+++ b/src/southbridge/amd/agesa/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
 
 static inline uint32_t smi_read32(uint8_t offset)
 {
-	return read32(SMI_BASE + offset);
+	return read32((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write32(uint8_t offset, uint32_t value)
 {
-	write32(SMI_BASE + offset, value);
+	write32((void *)(SMI_BASE + offset), value);
 }
 
 static inline uint16_t smi_read16(uint8_t offset)
 {
-	return read16(SMI_BASE + offset);
+	return read16((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write16(uint8_t offset, uint16_t value)
 {
-	write16(SMI_BASE + offset, value);
+	write16((void *)(SMI_BASE + offset), value);
 }
 
 void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 735ab7ed16..fe6ea507e3 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -53,12 +53,12 @@ static u32 spibar;
 
 static inline uint8_t spi_read(uint8_t reg)
 {
-	return read8(spibar + reg);
+	return read8((void *)(spibar + reg));
 }
 
 static inline void spi_write(uint8_t reg, uint8_t val)
 {
-	write8(spibar + reg, val);
+	write8((void *)(spibar + reg), val);
 }
 
 static void reset_internal_fifo_pointer(void)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 718b40bf9d..d75723ce65 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -42,7 +42,7 @@ static void lpc_init(struct device *dev)
 	byte |= 1;
 	pci_write_config8(dev, 0x4B, byte);
 	/* Don't rename IO APIC */
-	setup_ioapic(IO_APIC_ADDR, 0);
+	setup_ioapic(VIO_APIC_VADDR, 0);
 
 	/* posted memory write enable */
 	byte = pci_read_config8(dev, 0x46);
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index 5352705c6c..21df6c05d6 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -11,7 +11,7 @@
 #include "amd8111.h"
 
 
-#define CMD3		0x54
+#define CMD3		(0x54/(sizeof(u32)))
 
 typedef enum {
 	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
@@ -45,11 +45,11 @@ static void nic_init(struct device *dev)
 {
 	struct southbridge_amd_amd8111_config *conf;
 	struct resource *resource;
-	unsigned long mmio;
+	u8 *mmio;
 
 	conf = dev->chip_info;
 	resource = find_resource(dev, PCI_BASE_ADDRESS_0);
-	mmio = resource->base;
+	mmio = res2mmio(resource, 0, 0);
 
 	/* Hard Reset PHY */
 	printk(BIOS_DEBUG, "Resetting PHY... ");
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index b0ec2dcb2e..1e1357eba8 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -237,12 +237,12 @@ static void sb700_enable(device_t dev)
 				u32 ioapic_base;
 				printk(BIOS_DEBUG, "sm_init().\n");
 				ioapic_base = IO_APIC_ADDR;
-				clear_ioapic(ioapic_base);
+				clear_ioapic((void *)ioapic_base);
 				/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 				if (CONFIG_MAX_CPUS >= 16)
-					setup_ioapic(ioapic_base, 0);
+					setup_ioapic((void *)ioapic_base, 0);
 				else
-					setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
+					setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
 			}
 			break;
 
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 510bf234fb..e01793607b 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -353,18 +353,19 @@ static void sb800_enable(device_t dev)
 		break;
 
 	case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
-		clear_ioapic(IO_APIC_ADDR);
+		clear_ioapic(VIO_APIC_VADDR);
 #if CONFIG_CPU_AMD_AGESA
 		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-		setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+		setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 #else
 		/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
 #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16)
 		/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
-		setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+		setup_ioapic(VIO_APIC_VADDR,
+			     CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
 #elif (CONFIG_APIC_ID_OFFSET > 0)
 		/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
-		setup_ioapic(IO_APIC_ADDR, 0);
+		setup_ioapic(VIO_APIC_VADDR, 0);
 #else
 #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
 #endif
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index c84eee20c2..48820bc2bb 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -40,15 +40,17 @@ static u32 spibar;
 static void reset_internal_fifo_pointer(void)
 {
 	do {
-		write8(spibar + 2, read8(spibar + 2) | 0x10);
-	} while (read8(spibar + 0xD) & 0x7);
+		write8((void *)(spibar + 2),
+		       read8((void *)(spibar + 2)) | 0x10);
+	} while (read8((void *)(spibar + 0xD)) & 0x7);
 }
 
 static void execute_command(void)
 {
-	write8(spibar + 2, read8(spibar + 2) | 1);
+	write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1);
 
-	while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
+	while ((read8((void *)(spibar + 2)) & 1) &&
+	       (read8((void *)(spibar+3)) & 0x80));
 }
 
 void spi_init()
@@ -91,12 +93,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	readoffby1 = bytesout ? 0 : 1;
 
 	readwrite = (bytesin + readoffby1) << 4 | bytesout;
-	write8(spibar + 1, readwrite);
-	write8(spibar + 0, cmd);
+	write8((void *)(spibar + 1), readwrite);
+	write8((void *)(spibar + 0), cmd);
 
 	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesout; count++, dout++) {
-		write8(spibar + 0x0C, *(u8 *)dout);
+		write8((void *)(spibar + 0x0C), *(u8 *)dout);
 	}
 
 	reset_internal_fifo_pointer();
@@ -105,12 +107,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
 	reset_internal_fifo_pointer();
 	/* Skip the bytes we sent. */
 	for (count = 0; count < bytesout; count++) {
-		cmd = read8(spibar + 0x0C);
+		cmd = read8((void *)(spibar + 0x0C));
 	}
 
 	reset_internal_fifo_pointer();
 	for (count = 0; count < bytesin; count++, din++) {
-		*(u8 *)din = read8(spibar + 0x0C);
+		*(u8 *)din = read8((void *)(spibar + 0x0C));
 	}
 
 	return 0;
diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h
index 7a61569992..b6bde9fdd5 100644
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -3,7 +3,7 @@
 
 /* Hudson-2 ACPI PmIO Space Define */
 #define SB_ACPI_BASE_ADDRESS              0x0400
-#define ACPI_MMIO_BASE  0xFED80000
+#define ACPI_MMIO_BASE  ((u8 *)0xFED80000)
 #define SB_CFG_BASE     0x000   // DWORD
 #define GPIO_BASE       0x100   // BYTE
 #define SMI_BASE        0x200   // DWORD
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 3d873d0d8f..da79a670c4 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -429,7 +429,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb)
 
 static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 {
-	u32 bar;
+	void *bar;
 	msr_t msr;
 	device_t dev;
 
@@ -445,7 +445,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		/* write to clear diag register */
 		wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
 
-		bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+		bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
 		/* Make HCCPARAMS writable */
 		write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET);
@@ -457,7 +457,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	dev = dev_find_device(PCI_VENDOR_ID_AMD,
 			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
-		bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+		bar = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
 		write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET);
 
@@ -485,7 +485,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		dev = dev_find_device(PCI_VENDOR_ID_AMD,
 				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 		if (dev) {
-			bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			bar = (void *)pci_read_config32(dev,
+							PCI_BASE_ADDRESS_0);
 			write32(bar + UDCDEVCTL,
 			       read32(bar + UDCDEVCTL) | UDC_SD_SET);
 
@@ -494,7 +495,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		dev = dev_find_device(PCI_VENDOR_ID_AMD,
 				PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 		if (dev) {
-			bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			bar = (void *)pci_read_config32(dev,
+							PCI_BASE_ADDRESS_0);
 			write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET);
 			write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET);
 		}
diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
index 258267ed04..9deeb453ba 100644
--- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c
+++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 
 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	u32 base_regs = pci_ehci_base_regs(dev);
+	u8 *base_regs = pci_ehci_base_regs(dev);
 	u32 reg32;
 
 	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c
index e5382b410d..5c55065653 100644
--- a/src/southbridge/amd/pi/hudson/hudson.c
+++ b/src/southbridge/amd/pi/hudson/hudson.c
@@ -47,22 +47,22 @@ int acpi_get_sleep_type(void)
 
 void pm_write8(u8 reg, u8 value)
 {
-	write8(PM_MMIO_BASE + reg, value);
+	write8((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u8 pm_read8(u8 reg)
 {
-	return read8(PM_MMIO_BASE + reg);
+	return read8((void *)(PM_MMIO_BASE + reg));
 }
 
 void pm_write16(u8 reg, u16 value)
 {
-	write16(PM_MMIO_BASE + reg, value);
+	write16((void *)(PM_MMIO_BASE + reg), value);
 }
 
 u16 pm_read16(u16 reg)
 {
-	return read16(PM_MMIO_BASE + reg);
+	return read16((void *)(PM_MMIO_BASE + reg));
 }
 
 void hudson_enable(device_t dev)
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index d6ca215a6a..bc6564d1ec 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -82,7 +82,7 @@
 
 static void sm_init(device_t dev)
 {
-	setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS);
+	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
 }
 
 static int lsmbus_recv_byte(device_t dev)
diff --git a/src/southbridge/amd/pi/hudson/smi.h b/src/southbridge/amd/pi/hudson/smi.h
index de987a9274..2296c6eb26 100644
--- a/src/southbridge/amd/pi/hudson/smi.h
+++ b/src/southbridge/amd/pi/hudson/smi.h
@@ -36,22 +36,22 @@ enum smi_lvl {
 
 static inline uint32_t smi_read32(uint8_t offset)
 {
-	return read32(SMI_BASE + offset);
+	return read32((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write32(uint8_t offset, uint32_t value)
 {
-	write32(SMI_BASE + offset, value);
+	write32((void *)(SMI_BASE + offset), value);
 }
 
 static inline uint16_t smi_read16(uint8_t offset)
 {
-	return read16(SMI_BASE + offset);
+	return read16((void *)(SMI_BASE + offset));
 }
 
 static inline void smi_write16(uint8_t offset, uint16_t value)
 {
-	write16(SMI_BASE + offset, value);
+	write16((void *)(SMI_BASE + offset), value);
 }
 
 void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index c65f324832..de7a31913f 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -30,7 +30,7 @@
 #define HDA_ICII_BUSY (1 << 0)
 #define HDA_ICII_VALID (1 << 1)
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 dword;
 	int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
 {
 	u32 dword;
 
@@ -172,7 +172,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
  *  Wait 50usec for the codec to indicate it is ready
  *  no response would imply that the codec is non-operative
  */
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -194,7 +194,7 @@ static int wait_for_ready(u32 base)
  *  the previous command.  No response would imply that the code
  *  is non-operative
  */
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -211,7 +211,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
 {
 	u32 dword;
 	u32 *verb;
@@ -253,7 +253,7 @@ static void codec_init(u32 base, int addr)
 	printk(BIOS_DEBUG, "verb loaded!\n");
 }
 
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
 {
 	int i;
 	for (i = 2; i >= 0; i--) {
@@ -266,7 +266,7 @@ static void hda_init(struct device *dev)
 {
 	u8 byte;
 	u32 dword;
-	u32 base;
+	void *base;
 	struct resource *res;
 	u32 codec_mask;
 	device_t sm_dev;
@@ -300,8 +300,8 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "base = 0x%p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index a17aab8df7..2ff718230a 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -63,7 +63,7 @@ static void sata_init(struct device *dev)
 	u8 byte;
 	u16 word;
 	u32 dword;
-	u32 sata_bar5;
+	void *sata_bar5;
 	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
 	int i, j;
 
@@ -88,7 +88,7 @@ static void sata_init(struct device *dev)
 	pci_write_config8(sm_dev, 0xaf, byte);
 
 	/* get base address */
-	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
 	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
 	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
 	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -100,7 +100,7 @@ static void sata_init(struct device *dev)
 	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
 	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
 	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* SERR-Enable */
 	word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index a8e72c28f7..3ce5f020fa 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -57,7 +57,7 @@ static void sm_init(device_t dev)
 
 	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
-	clear_ioapic(ioapic_base);
+	clear_ioapic((void *)ioapic_base);
 
 	dword = pci_read_config8(dev, 0x62);
 	dword |= 1 << 2;
diff --git a/src/southbridge/amd/sb600/usb.c b/src/southbridge/amd/sb600/usb.c
index 137a8dac61..1b2b9ff1ae 100644
--- a/src/southbridge/amd/sb600/usb.c
+++ b/src/southbridge/amd/sb600/usb.c
@@ -88,13 +88,13 @@ static void usb_init2(struct device *dev)
 	u8 byte;
 	u16 word;
 	u32 dword;
-	u32 usb2_bar0;
+	void *usb2_bar0;
 	/* dword = pci_read_config32(dev, 0xf8); */
 	/* dword |= 40; */
 	/* pci_write_config32(dev, 0xf8, dword); */
 
-	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+	usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+	printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
 
 	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
 	dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c
index 3d23da0618..856d5bf1e5 100644
--- a/src/southbridge/amd/sb700/enable_usbdebug.c
+++ b/src/southbridge/amd/sb700/enable_usbdebug.c
@@ -39,7 +39,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 
 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	u32 base_regs = pci_ehci_base_regs(dev);
+	u8 *base_regs = pci_ehci_base_regs(dev);
 	u32 reg32;
 
 	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index 308b08cc32..f29ee3d612 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -30,7 +30,7 @@
 #define HDA_ICII_BUSY (1 << 0)
 #define HDA_ICII_VALID (1 << 1)
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 dword;
 	int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
 {
 	u32 dword;
 
@@ -94,7 +94,7 @@ no_codec:
  *  Wait 50usec for the codec to indicate it is ready
  *  no response would imply that the codec is non-operative
  */
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -116,7 +116,7 @@ static int wait_for_ready(u32 base)
  *  the previous command.  No response would imply that the code
  *  is non-operative
  */
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -133,7 +133,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
 {
 	u32 dword;
 
@@ -153,7 +153,7 @@ static void codec_init(u32 base, int addr)
 	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
 }
 
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
 {
 	int i;
 	for (i = 2; i >= 0; i--) {
@@ -166,7 +166,7 @@ static void hda_init(struct device *dev)
 {
 	u8 byte;
 	u32 dword;
-	u32 base;
+	void *base;
 	struct resource *res;
 	u32 codec_mask;
 	device_t sm_dev;
@@ -202,8 +202,8 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "base = 0x%p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 7fa924b8a3..9df6d481a9 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
 	u16 word;
 	u32 dword;
 	u8 rev_id;
-	u32 sata_bar5;
+	void *sata_bar5;
 	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
 	int i, j;
 
@@ -108,7 +108,7 @@ static void sata_init(struct device *dev)
 	rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
 
 	/* get base address */
-	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
 	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
 	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
 	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -120,7 +120,7 @@ static void sata_init(struct device *dev)
 	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
 	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
 	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* disable combined mode */
 	byte = pci_read_config8(sm_dev, 0xAD);
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 5aa4eb102d..1db637be37 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -50,14 +50,14 @@ static void sm_init(device_t dev)
 	u8 byte_old;
 	u8 rev;
 	u32 dword;
-	u32 ioapic_base;
+	void *ioapic_base;
 	u32 on;
 	u32 nmi_option;
 
 	printk(BIOS_INFO, "sm_init().\n");
 
 	rev = get_sb700_revision(dev);
-	ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
+	ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0));	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
 	/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
 	 * We need to check out why and change back. */
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c
index 77dcf2e2f6..dd8b390aed 100644
--- a/src/southbridge/amd/sb700/usb.c
+++ b/src/southbridge/amd/sb700/usb.c
@@ -81,7 +81,7 @@ static void usb_init(struct device *dev)
 static void usb_init2(struct device *dev)
 {
 	u32 dword;
-	u32 usb2_bar0;
+	void *usb2_bar0;
 	device_t sm_dev;
 	u8 rev;
 
@@ -92,8 +92,8 @@ static void usb_init2(struct device *dev)
 	/* dword |= 40; */
 	/* pci_write_config32(dev, 0xf8, dword); */
 
-	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+	usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+	printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
 
 	/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
 	dword = 0x00020F00;
diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c
index 74e3d3326e..ed1d88cd18 100644
--- a/src/southbridge/amd/sb800/enable_usbdebug.c
+++ b/src/southbridge/amd/sb800/enable_usbdebug.c
@@ -40,7 +40,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
 
 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
 {
-	u32 base_regs = pci_ehci_base_regs(dev);
+	u8 *base_regs = pci_ehci_base_regs(dev);
 	u32 reg32;
 
 	/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 5265684f29..d40d0886c8 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -30,7 +30,7 @@
 #define HDA_ICII_BUSY (1 << 0)
 #define HDA_ICII_VALID (1 << 1)
 
-static int set_bits(u32 port, u32 mask, u32 val)
+static int set_bits(void *port, u32 mask, u32 val)
 {
 	u32 dword;
 	int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
 	return 0;
 }
 
-static u32 codec_detect(u32 base)
+static u32 codec_detect(void *base)
 {
 	u32 dword;
 
@@ -96,7 +96,7 @@ no_codec:
  *  Wait 50usec for for the codec to indicate it is ready
  *  no response would imply that the codec is non-operative
  */
-static int wait_for_ready(u32 base)
+static int wait_for_ready(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -118,7 +118,7 @@ static int wait_for_ready(u32 base)
  *  the previous command.  No response would imply that the code
  *  is non-operative
  */
-static int wait_for_valid(u32 base)
+static int wait_for_valid(void *base)
 {
 	/* Use a 50 usec timeout - the Linux kernel uses the
 	 * same duration */
@@ -135,7 +135,7 @@ static int wait_for_valid(u32 base)
 	return -1;
 }
 
-static void codec_init(u32 base, int addr)
+static void codec_init(void *base, int addr)
 {
 	u32 dword;
 
@@ -155,7 +155,7 @@ static void codec_init(u32 base, int addr)
 	printk(BIOS_DEBUG, "%x(th) codec viddid: %08x\n", addr, dword);
 }
 
-static void codecs_init(u32 base, u32 codec_mask)
+static void codecs_init(void *base, u32 codec_mask)
 {
 	int i;
 	for (i = 3; i >= 0; i--) {
@@ -167,7 +167,7 @@ static void codecs_init(u32 base, u32 codec_mask)
 static void hda_init(struct device *dev)
 {
 	u32 dword;
-	u32 base;
+	void *base;
 	struct resource *res;
 	u32 codec_mask;
 
@@ -183,8 +183,8 @@ static void hda_init(struct device *dev)
 	if (!res)
 		return;
 
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "base = 0x%x\n", base);
+	base = res2mmio(res, 0, 0);
+	printk(BIOS_DEBUG, "base = 0x%p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index a1aa6e051e..cb685d1242 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -82,7 +82,7 @@ static void sata_init(struct device *dev)
 	u16 word;
 	u32 dword;
 	u8 rev_id;
-	u32 sata_bar5;
+	void *sata_bar5;
 	u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
 	int i, j;
 
@@ -98,7 +98,7 @@ static void sata_init(struct device *dev)
 	rev_id = pci_read_config8(sm_dev, 0x08) - 0x2F;
 
 	/* get base address */
-	sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
+	sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
 	sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
 	sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
 	sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
@@ -110,7 +110,7 @@ static void sata_init(struct device *dev)
 	printk(BIOS_SPEW, "sata_bar2=%x\n", sata_bar2);	/* 3040 */
 	printk(BIOS_SPEW, "sata_bar3=%x\n", sata_bar3);	/* 3080 */
 	printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk(BIOS_SPEW, "sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* SERR-Enable */
 	word = pci_read_config16(dev, 0x04);
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 662a82e4ef..2f5dfa127e 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -89,7 +89,7 @@ static void sm_init(device_t dev)
 	/* Don't rename APIC ID */
 	/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
 	 * We need to check out why and change back. */
-	clear_ioapic(IO_APIC_ADDR);
+	clear_ioapic(VIO_APIC_VADDR);
 	//setup_ioapic(IO_APIC_ADDR, 0);
 
 	/* enable serial irq */
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c
index 55be7b88f9..9cd6397d37 100644
--- a/src/southbridge/amd/sb800/usb.c
+++ b/src/southbridge/amd/sb800/usb.c
@@ -58,7 +58,7 @@ static void usb_init(struct device *dev)
 static void usb_init2(struct device *dev)
 {
 	u32 dword;
-	u32 usb2_bar0;
+	void *usb2_bar0;
 	device_t sm_dev;
 
 	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -68,8 +68,8 @@ static void usb_init2(struct device *dev)
 	/* dword |= 40; */
 	/* pci_write_config32(dev, 0xf8, dword); */
 
-	usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
-	printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
+	usb2_bar0 = (void *)(pci_read_config32(dev, 0x10) & ~0xFF);
+	printk(BIOS_INFO, "usb2_bar0=0x%p\n", usb2_bar0);
 
 	/* RPR7.3 Enables the USB PHY auto calibration resister to match 45ohm resistance */
 	dword = 0x00020F00;
diff --git a/src/southbridge/amd/sr5650/ht.c b/src/southbridge/amd/sr5650/ht.c
index 737eed28e6..816800f90e 100644
--- a/src/southbridge/amd/sr5650/ht.c
+++ b/src/southbridge/amd/sr5650/ht.c
@@ -128,7 +128,7 @@ static void sr5690_apic_init(struct device *dev)
 	dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
 	/* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the
 	 * 2nd one. We need to check if it also is on your board. */
-	setup_ioapic(dword, 1);
+	setup_ioapic((void *)dword, 1);
 }
 
 static void pcie_init(struct device *dev)