Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

7 files changed, 89 insertions, 20 deletions

diff --git a/src/southbridge/amd/amd8111/amd8111_lpc.c b/src/southbridge/amd/amd8111/amd8111_lpc.c
index 802f3c1044..c239f7e7cf 100644
--- a/src/southbridge/amd/amd8111/amd8111_lpc.c
+++ b/src/southbridge/amd/amd8111/amd8111_lpc.c
@@ -162,15 +162,26 @@ static void amd8111_lpc_read_resources(device_t dev)
 {
 	struct resource *res;
 
-	/* Get the normal pci resources of this device */
+	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-	
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void amd8111_lpc_enable_resources(device_t dev)
diff --git a/src/southbridge/amd/amd8131/amd8131_bridge.c b/src/southbridge/amd/amd8131/amd8131_bridge.c
index 9d85077668..29713a37c8 100644
--- a/src/southbridge/amd/amd8131/amd8131_bridge.c
+++ b/src/southbridge/amd/amd8131/amd8131_bridge.c
@@ -364,9 +364,6 @@ static void bridge_set_resources(struct device *dev)
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
diff --git a/src/southbridge/amd/amd8132/amd8132_bridge.c b/src/southbridge/amd/amd8132/amd8132_bridge.c
index 12ef26c171..8dc57d4510 100644
--- a/src/southbridge/amd/amd8132/amd8132_bridge.c
+++ b/src/southbridge/amd/amd8132/amd8132_bridge.c
@@ -350,9 +350,6 @@ static void bridge_set_resources(struct device *dev)
 		/* set the memory range */
 		dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 		res->flags |= IORESOURCE_STORED;
-		compute_allocate_resource(&dev->link[0], res,
-			IORESOURCE_MEM | IORESOURCE_PREFETCH,
-			IORESOURCE_MEM);
 		base = res->base;
 		end  = resource_end(res);
 		pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
diff --git a/src/southbridge/amd/cs5530/cs5530_isa.c b/src/southbridge/amd/cs5530/cs5530_isa.c
index 3d41d52939..a4d3b2eadb 100644
--- a/src/southbridge/amd/cs5530/cs5530_isa.c
+++ b/src/southbridge/amd/cs5530/cs5530_isa.c
@@ -25,6 +25,24 @@
 #include <device/pci_ids.h>
 #include "cs5530.h"
 
+static void cs5530_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void isa_init(struct device *dev)
 {
 	uint8_t reg8;
@@ -45,7 +63,7 @@ static void cs5530_pci_dev_enable_resources(device_t dev)
 }
 
 static struct device_operations isa_ops = {
-	.read_resources		= pci_dev_read_resources,
+	.read_resources		= cs5530_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= cs5530_pci_dev_enable_resources,
 	.init			= isa_init,
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index d1ec056a89..6f351ec48a 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -69,6 +69,24 @@ static void southbridge_enable(struct device *dev)
 	printk_spew("%s: dev is %p\n", __func__, dev);
 }
 
+static void cs5535_read_resources(device_t dev)
+{
+	struct resource* res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void cs5535_pci_dev_enable_resources(device_t dev)
 {
 	printk_spew("cs5535.c: %s()\n", __func__);
@@ -77,7 +95,7 @@ static void cs5535_pci_dev_enable_resources(device_t dev)
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources   = cs5535_read_resources,
 	.set_resources    = pci_dev_set_resources,
 	.enable_resources = cs5535_pci_dev_enable_resources,
 	.init             = southbridge_init,
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index 4169275b6f..002335d6b2 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -607,6 +607,25 @@ static void southbridge_init(struct device *dev)
 	}
 }
 
+static void cs5536_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	pci_dev_read_resources(dev);
+
+	res = new_resource(dev, 1);
+	res->base = 0x0UL;
+	res->size = 0x400UL;
+	res->limit = 0xffffUL;
+	res->flags = IORESOURCE_IO |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
 static void southbridge_enable(struct device *dev)
 {
 	printk_err("cs5536: %s: dev is %p\n", __func__, dev);
@@ -621,7 +640,7 @@ static void cs5536_pci_dev_enable_resources(device_t dev)
 }
 
 static struct device_operations southbridge_ops = {
-	.read_resources = pci_dev_read_resources,
+	.read_resources = cs5536_read_resources,
 	.set_resources = pci_dev_set_resources,
 	.enable_resources = cs5536_pci_dev_enable_resources,
 	.init = southbridge_init,
diff --git a/src/southbridge/amd/sb600/sb600_lpc.c b/src/southbridge/amd/sb600/sb600_lpc.c
index 50d00e25fa..b0cff6a583 100644
--- a/src/southbridge/amd/sb600/sb600_lpc.c
+++ b/src/southbridge/amd/sb600/sb600_lpc.c
@@ -70,14 +70,23 @@ static void sb600_lpc_read_resources(device_t dev)
 
 	pci_get_resource(dev, 0xA0); /* SPI ROM base address */
 
-	/* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O. */
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->flags =
-	    IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->flags =
-	    IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	compact_resources(dev);
 }
@@ -111,7 +120,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev)
 		for (child = dev->link[link].children; child;
 		     child = child->sibling) {
 			enable_resources(child);
-			if (child->have_resources
+			if (child->enabled
 			    && (child->path.type == DEVICE_PATH_PNP)) {
 				for (i = 0; i < child->resources; i++) {
 					struct resource *res;