AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper

Split FCH parts to southbridge/hudson.

Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7159
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

2 files changed, 94 insertions, 0 deletions

diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 98cac93ffd..84f0d3ecc0 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -10,6 +10,8 @@ ramstage-y += pci.c
 ramstage-y += pcie.c
 ramstage-y += sd.c
 
+ramstage-y += agesawrapper.c
+
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
 ramstage-y += reset.c
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c
new file mode 100644
index 0000000000..4de59b9ba3
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/agesa/agesawrapper.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "Filecode.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "Fch.h"
+#include <cpu/amd/agesa/s3_resume.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "hudson.h"
+
+extern UINT8 picr_data[0x54], intr_data[0x54];
+
+AGESA_STATUS agesawrapper_fchs3earlyrestore (void)
+{
+	FCH_DATA_BLOCK      FchParams;
+	AMD_CONFIG_PARAMS StdHeader;
+
+	StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+	StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+	StdHeader.AltImageBasePtr = 0;
+	StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	StdHeader.Func = 0;
+	StdHeader.ImageBasePtr = 0;
+
+	FchParams.StdHeader = &StdHeader;
+	s3_resume_init_data(&FchParams);
+	FchInitS3EarlyRestore(&FchParams);
+
+	return  AGESA_SUCCESS;
+}
+
+AGESA_STATUS agesawrapper_fchs3laterestore (void)
+{
+	FCH_DATA_BLOCK      FchParams;
+	AMD_CONFIG_PARAMS StdHeader;
+	UINT8 byte;
+
+	StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+	StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10;
+	StdHeader.AltImageBasePtr = 0;
+	StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	StdHeader.Func = 0;
+	StdHeader.ImageBasePtr = 0;
+
+	FchParams.StdHeader = &StdHeader;
+	s3_resume_init_data(&FchParams);
+	FchInitS3LateRestore(&FchParams);
+	/* PIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+		outb(byte, 0xC00);
+		outb(picr_data[byte], 0xC01);
+	}
+
+	/* APIC IRQ routine */
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
+
+	return AGESA_SUCCESS;
+}