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| author | Jacob Garber <jgarber1@ualberta.ca> | 2019-07-17 17:12:50 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-19 10:01:50 +0000 |
| commit | 52f3bd158a2edf92ec163912ee6b4053f976c636 (patch) | |
| tree | 663df3067ba02df9b8c5704c6a182e072a6ab744 /src/southbridge/amd | |
| parent | d92137adaba2898c86d696859c7c33f0a3bd7cbb (diff) | |
| download | coreboot-52f3bd158a2edf92ec163912ee6b4053f976c636.tar.xz | |
sb/amd/sb800: Remove bit shift that does nothing
This bit shift attempts to set bits 8 and 9 of the byte variable (counting
from 0). However, as the name suggests, this variable is only 8 bits
wide, so the shift does nothing. Reading section 7.5 of the
AMD SB800-Series Southbridges Register Programming Requirements manual,
bits 8 and 9 are already set by default, so we can remove the bit shift.
(Alternatively, we could try setting the corresponding bits one byte
higher in 0xF1 if needed.)
Change-Id: I645236441e02925ee01339378d213cb343027363
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229582
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb800/usb.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index bc8c1c664e..063750dc46 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -42,7 +42,6 @@ static void usb_init(struct device *dev) /* RPR 7.4 Enable the USB controller to get reset by any software that generate a PCIRst# condition */ byte = pm_ioread(0xF0); byte |= (1 << 2); - byte |= 3 << 8; /* rpr 7.5 */ pm_iowrite(0xF0, byte); /* RPR 7.9 Disable OHCI MSI Capability. */ |