diff options
| author | Scott Duplichan <scott@notabs.org> | 2011-05-15 21:41:00 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-05-15 21:41:00 +0000 |
| commit | be8fae1c710c71c9bf7479cf3d91a9f17a5594d1 (patch) | |
| tree | 9c45aedd5a3d25bf8243f0b0a8fc09aeb78d12e0 /src/southbridge/amd | |
| parent | f191c720389b5f4cffc3480096a11e2ff5a050b1 (diff) | |
| download | coreboot-be8fae1c710c71c9bf7479cf3d91a9f17a5594d1.tar.xz | |
Program the I/O APIC ID.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/late.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index 45689d7627..d8816fa1c8 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -352,6 +352,25 @@ static void sb800_enable(device_t dev) break; case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ + { + u8 byte; + u32 ioapic_base; + + printk(BIOS_INFO, "sm_init().\n"); + ioapic_base = 0xFEC00000; + clear_ioapic(ioapic_base); + /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ + #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) + /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ + setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + #elif (CONFIG_APIC_ID_OFFSET > 0) + /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ + setup_ioapic(ioapic_base, 0); + #else + #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" + #endif + } + break; case (0x14 << 3) | 1: /* 0:14:1 IDE */ |