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| author | Antonello Dettori <dev@dettori.io> | 2016-09-03 10:45:33 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-13 17:17:43 +0200 |
| commit | bf4224c723ce4a7ea115c7539447668e05510509 (patch) | |
| tree | 896b23b953d41c28df949d054d692c7f27d0458a /src/southbridge/amd | |
| parent | b0a60e5b212d7f98206a75f07edf0371d7cd9c1f (diff) | |
| download | coreboot-bf4224c723ce4a7ea115c7539447668e05510509.tar.xz | |
southbridge/amd/amd8111: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/amd/amd8111.
Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16473
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/amd8111/amd8111.h | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/early_ctrl.c | 8 | ||||
| -rw-r--r-- | src/southbridge/amd/amd8111/early_smbus.c | 2 |
3 files changed, 7 insertions, 5 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h index e877f2a13b..10df5906b0 100644 --- a/src/southbridge/amd/amd8111/amd8111.h +++ b/src/southbridge/amd/amd8111/amd8111.h @@ -3,7 +3,9 @@ #include "chip.h" +#ifndef __SIMPLE_DEVICE__ void amd8111_enable(device_t dev); +#endif #ifdef __PRE_RAM__ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index d84ef182fe..15f3123159 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -4,7 +4,7 @@ /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one 8111 on a hypertransport chain/bus. @@ -19,7 +19,7 @@ static unsigned get_sbdn(unsigned bus) static void enable_cf9_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; uint8_t byte; dev = PCI_DEV(sbbusn, sbdn+1, 3); //ACPI @@ -48,7 +48,7 @@ void hard_reset(void) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI @@ -61,7 +61,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) static void soft_reset_x(unsigned sbbusn, unsigned sbdn) { - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index aed4ebb46d..4c0ace5310 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -4,7 +4,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; uint8_t enable; dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); |