diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-30 11:37:14 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-07 12:35:33 +0000 |
| commit | d1a0c5770803e45dabecf6094fccb9895ea76d10 (patch) | |
| tree | 8c949297438a11ebdc39d0ea148ef24559917df8 /src/southbridge/amd | |
| parent | ab1d2ac626d0535191b5f612707ae8f22c46c538 (diff) | |
| download | coreboot-d1a0c5770803e45dabecf6094fccb9895ea76d10.tar.xz | |
usbdebug: Consolidate EHCI_BAR setup
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/enable_usbdebug.c | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/sb600/enable_usbdebug.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/sb700/enable_usbdebug.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/sb800/enable_usbdebug.c | 3 |
5 files changed, 0 insertions, 20 deletions
diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c index fce7f5b33b..4a37e557b6 100644 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c @@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - - pci_write_config32(dev, EHCI_BAR_INDEX, base); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/amd/pi/hudson/enable_usbdebug.c b/src/southbridge/amd/pi/hudson/enable_usbdebug.c index 787da6b676..cb6961ae40 100644 --- a/src/southbridge/amd/pi/hudson/enable_usbdebug.c +++ b/src/southbridge/amd/pi/hudson/enable_usbdebug.c @@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - - pci_write_config32(dev, EHCI_BAR_INDEX, base); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } diff --git a/src/southbridge/amd/sb600/enable_usbdebug.c b/src/southbridge/amd/sb600/enable_usbdebug.c index 797f6d2836..8b19cc41de 100644 --- a/src/southbridge/amd/sb600/enable_usbdebug.c +++ b/src/southbridge/amd/sb600/enable_usbdebug.c @@ -35,9 +35,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); } diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index 22f730f4ed..6d95b8ee4f 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -48,10 +48,4 @@ void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) { - /* Set the EHCI BAR address. */ - pci_write_config32(dev, EHCI_BAR_INDEX, base); - - /* Enable access to the EHCI memory space registers. */ - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); - } diff --git a/src/southbridge/amd/sb800/enable_usbdebug.c b/src/southbridge/amd/sb800/enable_usbdebug.c index 3959ea8013..8ef3151f13 100644 --- a/src/southbridge/amd/sb800/enable_usbdebug.c +++ b/src/southbridge/amd/sb800/enable_usbdebug.c @@ -53,7 +53,4 @@ void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) /* Enable all of the USB controllers */ outb(0xEF, PM_INDEX); outb(0x7F, PM_DATA); - - pci_write_config32(dev, EHCI_BAR_INDEX, base); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } |