diff options
| author | Nils Jacobs <njacobs8@hetnet.nl> | 2010-12-30 19:23:29 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-12-30 19:23:29 +0000 |
| commit | 8098e429445723a60cf7772777385259e2c498bb (patch) | |
| tree | 616064ee9a2e2ef9ac9a83dd3b03f5220baae484 /src/southbridge/amd | |
| parent | 8cf54c9f236afef6b74b6510983bd25e8536055a (diff) | |
| download | coreboot-8098e429445723a60cf7772777385259e2c498bb.tar.xz | |
Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cs5535/early_setup.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/cs5536/early_setup.c | 2 |
2 files changed, 2 insertions, 6 deletions
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c index 1a612cc55f..4a2e1b4965 100644 --- a/src/southbridge/amd/cs5535/early_setup.c +++ b/src/southbridge/amd/cs5535/early_setup.c @@ -107,15 +107,11 @@ static void cs5535_setup_cis_mode(void) { msr_t msr; - /* setup CPU interface serial to mode C on both sides */ + /* Setup CPU serial SouthBridge interface to mode C. */ msr = rdmsr(GLPCI_SB_CTRL); msr.lo &= ~0x18; msr.lo |= 0x10; wrmsr(GLPCI_SB_CTRL, msr); - //Only do this if we are building for 5535 - msr.lo = 0x2; - msr.hi = 0x0; - wrmsr(VIP_GIO_MSR_SEL, msr); } static void dummy(void) diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index 0a35964ef2..7d982433d4 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -145,7 +145,7 @@ static void cs5536_setup_cis_mode(void) { msr_t msr; - /* setup CPU interface serial to mode B to match CPU */ + /* Setup CPU serial SouthBridge interface to mode C. */ msr = rdmsr(GLPCI_SB_CTRL); msr.lo &= ~0x18; msr.lo |= 0x10; |