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| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 14:36:13 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-11-27 11:28:38 +0100 |
| commit | 8be82e1017970e0b86e44b2838ee77d1f100b0c5 (patch) | |
| tree | e58b8c1cb216181d396fb943f4dfd86cef4d0193 /src/southbridge/amd | |
| parent | 32960e30f08f678355b20b5702e8028351a7275e (diff) | |
| download | coreboot-8be82e1017970e0b86e44b2838ee77d1f100b0c5.tar.xz | |
southbridge/amd/agesa/hudson/pci.c: Use DEVICE_NOOP macro
Change-Id: I39edaaed67f45e7c56ec02c2aac2a4c5e1b63bc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7586
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/pci.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index e8836e4c7d..49e2ba6c47 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -27,9 +27,6 @@ #include <southbridge/amd/amd_pci_util.h> #include <bootstate.h> -static void pci_init(struct device *dev) -{ -} /* * Update the PCI devices with a valid IRQ number @@ -61,7 +58,7 @@ static struct device_operations pci_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = pci_init, + .init = DEVICE_NOOP, .scan_bus = pci_scan_bridge, .reset_bus = pci_bus_reset, .ops_pci = &lops_pci, |