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authorLi-Ta Lo <ollie@lanl.gov>2004-05-10 19:33:27 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-05-10 19:33:27 +0000
commita60bf67b32090ef97cfb78e7968f5ece9e344063 (patch)
treeb62c8ad7cf1a7bccf6779b1402c65d0beeb4e33e /src/southbridge/amd
parent9f0d0f9669a2421398700292dbb377eff125c4fe (diff)
downloadcoreboot-a60bf67b32090ef97cfb78e7968f5ece9e344063.tar.xz
fixed minor bug in APG bridge code. Use AGP_APERTURE_SIZE instead of IOMMU_APERTURE_SIZE
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1553 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/amd8151/amd8151_agp3.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index a4d4dce1a1..b58f7926d4 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -12,15 +12,17 @@
static void agp3bridge_init(device_t dev)
{
uint8_t byte;
-
+
+ /* Enable BM and IO */
byte = pci_read_config32(dev, 0x04);
byte |= 0x07;
pci_write_config8(dev, 0x04, byte);
-
- byte = pci_read_config32(dev, 0xce);
+
+ /* Eable VGA/ISA decoding */
+ byte = pci_read_config32(dev, 0x3e);
byte |= 3<<2;
- pci_write_config8(dev, 0xce, byte);
-
+ pci_write_config8(dev, 0x3e, byte);
+
return;
}
@@ -38,7 +40,6 @@ static struct pci_driver agp3bridge_driver __pci_driver = {
.device = 0x7455, // AGP Bridge
};
-
static void agp3dev_enable(device_t dev)
{
uint32_t value;