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| author | Marc Jones <marcj303@gmail.com> | 2010-03-09 21:51:31 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2010-03-09 21:51:31 +0000 |
| commit | a51021b9a11ab0910fb3fa827c0dd094a89960bb (patch) | |
| tree | 5e6ca5ebd31db9fc2a3ae2612e50f5db4261e0cc /src/southbridge/amd | |
| parent | 2140575066d3890a74c2820932af9bf26a7b0adb (diff) | |
| download | coreboot-a51021b9a11ab0910fb3fa827c0dd094a89960bb.tar.xz | |
sb600 has problems with the virtual wire mode setup in setup_ioapic(). It causes problems when interrupts are enabled (specifically timer).
Previously the sb600 setup was equivalent to clear_ioapic(), so that is what we will do for now.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/sb600/sb600_sm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index 318c370151..20b266df91 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -58,7 +58,7 @@ static void sm_init(device_t dev) ioapic_base = pci_read_config32(dev, 0x74) & (0xffffffe0); /* some like mem resource, but does not have enable bit */ /* Don't rename APIC ID */ - setup_ioapic(ioapic_base, 0); + clear_ioapic(ioapic_base); dword = pci_read_config8(dev, 0x62); dword |= 1 << 2; |