sb/amd: Use simple PCI IO config access

Call the simple PCI config accessors directly.

Change-Id: I4aa0669179d6b01ab0713fd2a8b3cf4baf6e572f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 29 insertions, 25 deletions

diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index d2a0b16741..6478ade955 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -30,32 +30,33 @@ void static rs780_config_misc_clk(struct device *nb_dev)
 	u32 reg;
 	u16 word;
 	u8 byte;
+	pci_devfn_t d0f1 = PCI_DEV(0, 0, 1);
 
 	reg = pci_read_config32(nb_dev, 0x4c);
 	reg |= 1 << 0;
 	pci_write_config32(nb_dev, 0x4c, reg);
 
-	word = pci_cf8_conf1.read16(0, 1, 0xf8);
+	word = pci_io_read_config16(d0f1, 0xf8);
 	word &= 0xf00;
-	pci_cf8_conf1.write16(0, 1, 0xf8, word);
+	pci_io_write_config16(d0f1, 0xf8, word);
 
-	word = pci_cf8_conf1.read16(0, 1, 0xe8);
+	word = pci_io_read_config16(d0f1, 0xe8);
 	word &= ~((1 << 12) | (1 << 13) | (1 << 14));
 	word |= 1 << 13;
-	pci_cf8_conf1.write16(0, 1, 0xe8, word);
+	pci_io_write_config16(d0f1, 0xe8, word);
 
-	reg =  pci_cf8_conf1.read32(0, 1, 0x94);
+	reg =  pci_io_read_config32(d0f1, 0x94);
 	reg &= ~((1 << 16) | (1 << 24) | (1 << 28));
-	pci_cf8_conf1.write32(0, 1, 0x94, reg);
+	pci_io_write_config32(d0f1, 0x94, reg);
 
-	reg = pci_cf8_conf1.read32(0, 1, 0x8c);
+	reg = pci_io_read_config32(d0f1, 0x8c);
 	reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25));
 	reg |= 1 << 13;
-	pci_cf8_conf1.write32(0, 1, 0x8c, reg);
+	pci_io_write_config32(d0f1, 0x8c, reg);
 
-	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
+	reg = pci_io_read_config32(d0f1, 0xcc);
 	reg |= 1 << 24;
-	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
+	pci_io_write_config32(d0f1, 0xcc, reg);
 
 	reg = nbmc_read_index(nb_dev, 0x7a);
 	reg &= ~0x3f;
@@ -64,31 +65,31 @@ void static rs780_config_misc_clk(struct device *nb_dev)
 	set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
 	nbmc_write_index(nb_dev, 0x7a, reg);
 	/* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */
-	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
+	reg = pci_io_read_config32(d0f1, 0xcc);
 	reg &= ~(1 << 23);
 	reg |= 1 << 24;
-	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
+	pci_io_write_config32(d0f1, 0xcc, reg);
 
 	/* Programming NB CLK table. */
-	byte = pci_cf8_conf1.read8(0, 1, 0xe0);
+	byte = pci_io_read_config8(d0f1, 0xe0);
 	byte |= 0x01;
-	pci_cf8_conf1.write8(0, 1, 0xe0, byte);
+	pci_io_write_config8(d0f1, 0xe0, byte);
 
 #if 0
 	/* Powerdown reference clock to graphics core PLL in northbridge only mode */
-	reg = pci_cf8_conf1.read32(0, 1, 0x8c);
+	reg = pci_io_read_config32(d0f1, 0x8c);
 	reg |= 1 << 21;
-	pci_cf8_conf1.write32(0, 1, 0x8c, reg);
+	pci_io_write_config32(d0f1, 0x8c, reg);
 
 	/* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */
-	reg = pci_cf8_conf1.read32(0, 1, 0xcc);
+	reg = pci_io_read_config32(d0f1, 0xcc);
 	reg |= (1 << 23) | (1 << 24);
-	pci_cf8_conf1.write32(0, 1, 0xcc, reg);
+	pci_io_write_config32(d0f1, 0xcc, reg);
 
 	/* Powerdown clock to memory controller in northbridge only mode */
-	byte = pci_cf8_conf1.read8(0, 1, 0xe4);
+	byte = pci_io_read_config8(d0f1, 0xe4);
 	byte |= 1 << 0;
-	pci_cf8_conf1.write8(0, 1, 0xe4, reg);
+	pci_io_write_config8(d0f1, 0xe4, reg);
 
 	/* CLKCFG:0xE8 Bit[17] = 0x1	 Powerdown clock to IOC GFX block in no external graphics mode */
 	/* TODO: */
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 763dd014af..f87fadbb08 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -893,7 +893,10 @@ void pcie_config_misc_clk(struct device *nb_dev)
 	reg |= 1 << 0;
 	pci_write_config32(nb_dev, 0x4c, reg);
 
-#if 0				/* TODO: Check the mics clock later. */
+#if 0
+	/* TODO: Check the mics clock later. */
+	pci_devfn_t d0f1 = PCI_DEV(0, 0, 1);
+
 	if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
 		/* TXCLK Clock Gating */
 		set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
@@ -901,9 +904,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(0, 1, 0x94);
+		reg = pci_io_read_config32(d0f1, 0x94);
 		reg &= ~(1 << 16);
-		pci_cf8_conf1.write32(0, 1, 0x94, reg);
+		pci_io_write_config32(d0f1, 0x94, reg);
 	}
 
 	if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
@@ -913,9 +916,9 @@ void pcie_config_misc_clk(struct device *nb_dev)
 		set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
 
 		/* LCLK Clock Gating */
-		reg =  pci_cf8_conf1.read32(0, 1, 0x94);
+		reg = pci_io_read_config32(d0f1, 0x94);
 		reg &= ~(1 << 24);
-		pci_cf8_conf1.write32(0, 1, 0x94, reg);
+		pci_io_write_config32(d0f1, 0x94, reg);
 	}
 #endif