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authorzbao <fishbaozi@gmail.com>2012-08-03 16:58:53 +0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2012-08-05 07:01:26 +0200
commit366f0fc30a6b0439cfa2867b3d435975512bd9b8 (patch)
treecd2bd91a5648b3aef503014e4c46c9f95aa04da1 /src/southbridge/amd
parentcc3b18843f5db9ccdb2c8cd609897e2560f47a92 (diff)
downloadcoreboot-366f0fc30a6b0439cfa2867b3d435975512bd9b8.tar.xz
AMD SB: Call the rtc update if needed (Propagation)
Apply the change http://review.coreboot.org/1390 to all the AMD southbridge. Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1406 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c12
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c12
-rw-r--r--src/southbridge/amd/cimx/sb900/late.c3
-rw-r--r--src/southbridge/amd/sb600/lpc.c1
-rw-r--r--src/southbridge/amd/sb700/lpc.c2
-rw-r--r--src/southbridge/amd/sb800/lpc.c2
6 files changed, 30 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 4e51e0a3e3..be2b8cd863 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -23,6 +23,7 @@
#include <device/pci_ids.h>
#include <arch/ioapic.h>
#include <device/smbus.h> /* smbus_bus_operations */
+#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
#include "lpc.h" /* lpc_read_resources */
#include "Platform.h" /* Platfrom Specific Definitions */
@@ -72,11 +73,20 @@ static void lpc_enable_resources(device_t dev)
printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
}
+static void lpc_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
+
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
+ printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
+}
+
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = lpc_enable_resources,
- .init = 0,
+ .init = lpc_init,
.scan_bus = scan_static_bus,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 0ce82b3307..7286a6d16d 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -23,6 +23,7 @@
#include <device/pci_ids.h>
#include <arch/ioapic.h>
#include <device/smbus.h> /* smbus_bus_operations */
+#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
#include <arch/acpi.h>
#include "lpc.h" /* lpc_read_resources */
@@ -120,11 +121,20 @@ static struct pci_operations lops_pci = {
.set_subsystem = pci_dev_set_subsystem,
};
+static void lpc_init(device_t dev)
+{
+ printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
+
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
+ printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
+}
+
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = 0,
+ .init = lpc_init,
.scan_bus = scan_static_bus,
.ops_pci = &lops_pci,
};
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 71c65e31c6..85485edfb6 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -22,6 +22,7 @@
#include <device/pci.h> /* device_operations */
#include <device/pci_ids.h>
#include <device/smbus.h> /* smbus_bus_operations */
+#include <pc80/mc146818rtc.h>
#include <console/console.h> /* printk */
#include "lpc.h" /* lpc_read_resources */
#include "SbPlatform.h" /* Platfrom Specific Definitions */
@@ -98,6 +99,8 @@ static void lpc_init(device_t dev)
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
}
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 6f16ea81c7..22945a7e8e 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -60,6 +60,7 @@ static void lpc_init(device_t dev)
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index c968927854..be940e3d2f 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -81,6 +81,8 @@ static void lpc_init(device_t dev)
printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type);
}
#endif
+
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
}
void set_cbmem_toc(struct cbmem_entry *toc)
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 4e2031f9c5..3cb0789939 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -67,6 +67,8 @@ static void lpc_init(device_t dev)
byte = pci_read_config8(dev, 0xBB);
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
+
+ rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
}
static void sb800_lpc_read_resources(device_t dev)