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authorWANG Siyuan <wangsiyuanbuaa@gmail.com>2013-12-02 10:18:04 +0800
committerRudolf Marek <r.marek@assembler.cz>2014-02-01 19:07:19 +0100
commit55f9a731b8c6bec598871943bd613187c8546ac3 (patch)
tree438036a3416ed2d246134326acfbf62087f066f6 /src/southbridge/amd
parent62adc4c6101749d59bdcc36135556fc2d2482131 (diff)
downloadcoreboot-55f9a731b8c6bec598871943bd613187c8546ac3.tar.xz
AMD hudson and yangtze: add IMC fan control support
imc_reg_init: init fan control related registers. enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable it here. Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91 Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/4300 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/agesa/hudson/Makefile.inc3
-rw-r--r--src/southbridge/amd/agesa/hudson/imc.c89
-rw-r--r--src/southbridge/amd/agesa/hudson/imc.h26
3 files changed, 118 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index 6a097fccac..54a93d23f8 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -19,6 +19,9 @@ romstage-y += early_setup.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c
+romstage-y += imc.c
+ramstage-y += imc.c
+
# ROMSIG At ROMBASE + 0x20000:
# +-----------+---------------+----------------+------------+
# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM |
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c
new file mode 100644
index 0000000000..af9e865b90
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/imc.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "imc.h"
+#include <arch/io.h>
+#include <delay.h>
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Fch.h"
+#include "FchCommonCfg.h"
+#include "FchPlatform.h"
+
+void imc_reg_init(void)
+{
+ /* Init Power Management Block 2 (PM2) Registers.
+ * Check BKDG for AMD Family 16h for details. */
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x00, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x01, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x02, 0xf7);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
+
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x13, 0xff);
+ write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff);
+#endif
+
+#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ UINT8 PciData;
+ PCI_ADDR PciAddress;
+ AMD_CONFIG_PARAMS StdHeader;
+ PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 0x3, 0x1E4);
+ LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
+ PciData &= (UINT8)0x8F;
+ PciData |= 0x10;
+ LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
+#endif
+}
+
+#ifndef __PRE_RAM__
+void enable_imc_thermal_zone(void)
+{
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT8 FunNum;
+ UINT8 regs[9];
+ int i;
+
+ regs[0] = 0;
+ regs[1] = 0;
+ FunNum = Fun_80;
+ for (i=0; i<=1; i++)
+ WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck(&StdHeader);
+
+ for (i=2; i<=9; i++)
+ ReadECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+
+ /* enable thermal zone 0 */
+ regs[2] |= 1;
+ regs[0] = 0;
+ regs[1] = 0;
+ FunNum = Fun_81;
+ for (i=0; i<=9; i++)
+ WriteECmsg(MSG_REG0 + i, AccessWidth8, &regs[i], &StdHeader);
+ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number
+ WaitForEcLDN9MailboxCmdAck(&StdHeader);
+}
+#endif
diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h
new file mode 100644
index 0000000000..d348319dee
--- /dev/null
+++ b/src/southbridge/amd/agesa/hudson/imc.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef HUDSON_IMC_H
+#define HUDSON_IMC_H
+
+void imc_reg_init(void);
+void enable_imc_thermal_zone(void);
+
+#endif