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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-30 06:51:28 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-31 03:40:16 +0000
commit8251fa0eb0ac5c073be47793fe5ecc9102d34d6a (patch)
tree3be5eec3f4587f093ededfef260d918953500482 /src/southbridge/amd
parentf8307c3bb4260303db209dc94e4d4f4b4d131632 (diff)
downloadcoreboot-8251fa0eb0ac5c073be47793fe5ecc9102d34d6a.tar.xz
AGESA binaryPI: Remove dependency on K8 headers
The included .c file also pulled in ancient files amdk8/pre_f.h and amdk8/raminit.h Do a dirty copy-paste to work around that. Change-Id: Ie89a5f91d5234f1ef334d30a43dd56e0b722b5ac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/agesa/hudson/reset.c13
-rw-r--r--src/southbridge/amd/pi/hudson/reset.c14
2 files changed, 25 insertions, 2 deletions
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index e3f36f3309..315456dbd6 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -19,7 +19,18 @@
#include <arch/io.h>
#include <reset.h>
-#include <northbridge/amd/amdk8/reset_test.c>
+#define HT_INIT_CONTROL 0x6c
+#define HTIC_ColdR_Detect (1<<4)
+#define HTIC_BIOSR_Detect (1<<5)
+#define HTIC_INIT_Detect (1<<6)
+
+static void set_bios_reset(void)
+{
+ u32 htic;
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+}
void do_hard_reset(void)
{
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index e3f36f3309..f80e2d4c32 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -19,7 +19,19 @@
#include <arch/io.h>
#include <reset.h>
-#include <northbridge/amd/amdk8/reset_test.c>
+#define HT_INIT_CONTROL 0x6c
+#define HTIC_ColdR_Detect (1<<4)
+#define HTIC_BIOSR_Detect (1<<5)
+#define HTIC_INIT_Detect (1<<6)
+
+static void set_bios_reset(void)
+{
+ u32 htic;
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+}
+
void do_hard_reset(void)
{