diff options
| author | Kerry She <kerry.she@amd.com> | 2011-06-01 01:56:49 +0000 |
|---|---|---|
| committer | Kerry She <Kerry.She@amd.com> | 2011-06-01 01:56:49 +0000 |
| commit | 991f8808933a8b528108dcd48a029ebf40b05c6b (patch) | |
| tree | d08e8791ab01d76df137a984f0fed1a91cab5632 /src/southbridge/amd | |
| parent | b2ecd8151481af7c5a74ed61967ad9698486253e (diff) | |
| download | coreboot-991f8808933a8b528108dcd48a029ebf40b05c6b.tar.xz | |
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/cfg.h | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx_wrapper/sb800/late.c | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h b/src/southbridge/amd/cimx_wrapper/sb800/cfg.h index e89daca381..581fc661ea 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/cfg.h +++ b/src/southbridge/amd/cimx_wrapper/sb800/cfg.h @@ -100,7 +100,7 @@ * @breif INCHIP Sata Controller */ #ifndef SATA_CONTROLLER - #define SATA_CONTROLLER ENABLED + #define SATA_CONTROLLER CIMX_OPTION_ENABLED #endif /** @@ -202,7 +202,7 @@ * @def GPP_CONTROLLER */ #ifndef GPP_CONTROLLER - #define GPP_CONTROLLER ENABLED + #define GPP_CONTROLLER CIMX_OPTION_ENABLED #endif /** diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c index e375b23dd8..de1637a0c5 100644 --- a/src/southbridge/amd/cimx_wrapper/sb800/late.c +++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c @@ -21,6 +21,7 @@ #include <device/device.h> /* device_t */ #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> +#include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ #include "lpc.h" /* lpc_read_resources */ @@ -328,13 +329,13 @@ static void sb800_enable(device_t dev) switch (dev->path.pci.devfn) { case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY @@ -352,11 +353,10 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { - u8 byte; u32 ioapic_base; printk(BIOS_INFO, "sm_init().\n"); - ioapic_base = 0xFEC00000; + ioapic_base = IO_APIC_ADDR; clear_ioapic(ioapic_base); /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) @@ -374,9 +374,9 @@ static void sb800_enable(device_t dev) case (0x14 << 3) | 1: /* 0:14:1 IDE */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; } sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; |