summaryrefslogtreecommitdiff
path: root/src/southbridge/amd
diff options
context:
space:
mode:
authorMike Loptien <mike.loptien@se-eng.com>2013-02-25 10:41:28 -0700
committerDave Frodin <dave.frodin@se-eng.com>2013-02-25 19:28:43 +0100
commita96d24d672abfd2ce91caa2d762fdce3d67da600 (patch)
treeff526a651f8b2975193f6f0b8e56830fa9b38271 /src/southbridge/amd
parent7675d8a481c6cbeba418f00f2eb733d904171a41 (diff)
downloadcoreboot-a96d24d672abfd2ce91caa2d762fdce3d67da600.tar.xz
AMD Southbridge: Add RTC init to lpc_init
Adding RTC init code to the Southbridge initialization code in 'lpc_init'. This initializes the RTC so that the Date Alarm register is set to a valid value (0x00) at startup. By setting the Date Alarm register to 0x00, it does not get evaluated along with the seconds, minutes, and hours when running 'fwts s3'. Information about fwts (Firmware Test Suite) can be found here: https://wiki.ubuntu.com/Kernel/Reference/fwts This is the same edit made to the CIMX SB800 titled 'AMD/Persimmon: Add RTC init to CIMX SB800' with commit ID: c4d3d which can be viewed here: http://review.coreboot.org/#/c/2488/ Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90 Signed-off-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/2510 Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c7
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c7
-rw-r--r--src/southbridge/amd/cimx/sb900/late.c7
3 files changed, 21 insertions, 0 deletions
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 86e937e569..aad4eb9efa 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -69,6 +69,13 @@ static void lpc_init(device_t dev)
pci_write_config8(dev, 0xBB, byte);
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index be2b8cd863..4c5dde9199 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -79,6 +79,13 @@ static void lpc_init(device_t dev)
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
+
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 85485edfb6..65cea695ae 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -101,6 +101,13 @@ static void lpc_init(device_t dev)
//- hpetInit(sb_config, &(sb_config->BuildParameters));
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
+
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
}