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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 23:11:50 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-20 13:19:05 +0000 |
| commit | e8e2e3e00d6a4184419c52c3395c72ad4ba95eac (patch) | |
| tree | c1c77e905d3d1a1220cc2b01852239ec544ae812 /src/southbridge/amd | |
| parent | 2e5e99c48ce374e8ad1d92a77e54c5e22a770f0b (diff) | |
| download | coreboot-e8e2e3e00d6a4184419c52c3395c72ad4ba95eac.tar.xz | |
sb/intel/i82371eb: Declare reset register in FADT
According to Intel Order Number 290562 (PIIX4 datasheet), 0xcf9 is the
reset register, and setting bits 1 and 2 will result in a hard reset.
Change-Id: Id5ada6a10b2269d51908c6a5fd7745ef6c33a29a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/amd')
0 files changed, 0 insertions, 0 deletions