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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-19 08:29:41 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 02:08:42 +0000
commitc99d3afe3e78565937c215f882bd4b7fc586f66e (patch)
tree4883a3ae5d65c369c5c85abae73cc1946f0a2c76 /src/southbridge/amd
parent1e02d73c73f6f59f66c198b8c2afe77b0a730b01 (diff)
downloadcoreboot-c99d3afe3e78565937c215f882bd4b7fc586f66e.tar.xz
amdfam10: Remove use of __PRE_RAM__
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/amd8111/amd8111.h7
-rw-r--r--src/southbridge/amd/amd8111/ide.c1
-rw-r--r--src/southbridge/amd/amd8111/nic.c2
-rw-r--r--src/southbridge/amd/sb700/ide.c1
-rw-r--r--src/southbridge/amd/sb700/sb700.c1
-rw-r--r--src/southbridge/amd/sb700/sb700.h30
-rw-r--r--src/southbridge/amd/sb800/ide.c1
-rw-r--r--src/southbridge/amd/sb800/sata.c1
-rw-r--r--src/southbridge/amd/sb800/sb800.c1
-rw-r--r--src/southbridge/amd/sb800/sb800.h9
10 files changed, 22 insertions, 32 deletions
diff --git a/src/southbridge/amd/amd8111/amd8111.h b/src/southbridge/amd/amd8111/amd8111.h
index a984143a17..447edf9b4c 100644
--- a/src/southbridge/amd/amd8111/amd8111.h
+++ b/src/southbridge/amd/amd8111/amd8111.h
@@ -14,14 +14,9 @@
#ifndef AMD8111_H
#define AMD8111_H
-#include "chip.h"
+#include <device/device.h>
-#ifndef __SIMPLE_DEVICE__
void amd8111_enable(struct device *dev);
-#endif
-
-#ifdef __PRE_RAM__
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-#endif
#endif /* AMD8111_H */
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index 420e28e157..49f9d154f8 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -17,6 +17,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "amd8111.h"
+#include "chip.h"
static void ide_init(struct device *dev)
{
diff --git a/src/southbridge/amd/amd8111/nic.c b/src/southbridge/amd/amd8111/nic.c
index adf8af0d43..a4abd0360a 100644
--- a/src/southbridge/amd/amd8111/nic.c
+++ b/src/southbridge/amd/amd8111/nic.c
@@ -21,7 +21,7 @@
#include <device/mmio.h>
#include <delay.h>
#include "amd8111.h"
-
+#include "chip.h"
#define CMD3 0x54
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 0b11db3c86..070ee67d9c 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -22,6 +22,7 @@
#include <types.h>
#include "sb700.h"
+#include "chip.h"
static void ide_init(struct device *dev)
{
diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c
index 1836f34eb0..1eaf347dcc 100644
--- a/src/southbridge/amd/sb700/sb700.c
+++ b/src/southbridge/amd/sb700/sb700.c
@@ -22,6 +22,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "sb700.h"
+#include "chip.h"
static struct device *find_sm_dev(struct device *dev, u32 devfn)
{
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 156522e579..4b863a0778 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -17,7 +17,8 @@
#ifndef SB700_H
#define SB700_H
-#include "chip.h"
+#include <types.h>
+#include <device/device.h>
/* Power management index/data registers */
#define BIOSRAM_INDEX 0xcd4
@@ -37,14 +38,12 @@
#define ACPI_CPU_CONTROL (SB700_ACPI_IO_BASE + 0x08) /* 6 bytes */
#define ACPI_CPU_P_LVL2 (ACPI_CPU_CONTROL + 0x4) /* 1 byte */
-extern void pm_iowrite(u8 reg, u8 value);
-extern u8 pm_ioread(u8 reg);
-extern void pm2_iowrite(u8 reg, u8 value);
-extern u8 pm2_ioread(u8 reg);
-#ifndef __SIMPLE_DEVICE__
-extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
- u32 val);
-#endif
+void pm_iowrite(u8 reg, u8 value);
+u8 pm_ioread(u8 reg);
+void pm2_iowrite(u8 reg, u8 value);
+u8 pm2_ioread(u8 reg);
+
+void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
#define REV_SB700_A11 0x11
#define REV_SB700_A12 0x12
@@ -58,11 +57,7 @@ extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
* The differentiate is 0x28, isn't it? */
#define get_sb700_revision(sm_dev) (pci_read_config8((sm_dev), 0x08) - 0x28)
-#ifndef __SIMPLE_DEVICE__
-void sb7xx_51xx_enable(struct device *dev);
-#endif
-#ifdef __PRE_RAM__
void sb7xx_51xx_lpc_port80(void);
void sb7xx_51xx_pci_port80(void);
void sb7xx_51xx_lpc_init(void);
@@ -71,14 +66,12 @@ void sb7xx_51xx_disable_wideio(u8 wio_index);
void sb7xx_51xx_early_setup(void);
void sb7xx_51xx_before_pci_init(void);
uint16_t sb7xx_51xx_decode_last_reset(void);
-#else
-#include <device/pci.h>
-#include <device/pci_ops.h>
+
+
/* allow override in mainboard.c */
void sb7xx_51xx_setup_sata_phys(struct device *dev);
void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);
-
-#endif
+void sb7xx_51xx_enable(struct device *dev);
void set_lpc_sticky_ctl(bool enable);
@@ -86,4 +79,5 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn);
+
#endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
index fddb48c8d2..77e2f5ef1d 100644
--- a/src/southbridge/amd/sb800/ide.c
+++ b/src/southbridge/amd/sb800/ide.c
@@ -18,6 +18,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "sb800.h"
+#include "chip.h"
static void ide_init(struct device *dev)
{
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 48a8740122..8611272d78 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -22,6 +22,7 @@
#include <arch/io.h>
#include <device/mmio.h>
#include "sb800.h"
+#include "chip.h"
static int sata_drive_detect(int portnum, u16 iobar)
{
diff --git a/src/southbridge/amd/sb800/sb800.c b/src/southbridge/amd/sb800/sb800.c
index 801cc65e4a..c7efaec732 100644
--- a/src/southbridge/amd/sb800/sb800.c
+++ b/src/southbridge/amd/sb800/sb800.c
@@ -23,6 +23,7 @@
#include <device/pci_ops.h>
#include "sb800.h"
#include "smbus.h"
+#include "chip.h"
static struct device *find_sm_dev(struct device *dev, u32 devfn)
{
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index 3715a3ac1c..07c78ec429 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -17,7 +17,8 @@
#ifndef SB800_H
#define SB800_H
-#include "chip.h"
+#include <types.h>
+#include <device/device.h>
/* Power management index/data registers */
#define BIOSRAM_INDEX 0xcd4
@@ -42,15 +43,11 @@ u8 pm_ioread(u8 reg);
void pm2_iowrite(u8 reg, u8 value);
u8 pm2_ioread(u8 reg);
-#ifndef __SIMPLE_DEVICE__
void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val);
-#endif
#define REV_SB800_A11 0x11
#define REV_SB800_A12 0x12
-
-#ifdef __PRE_RAM__
void sb800_lpc_port80(void);
void sb800_pci_port80(void);
void sb800_clk_output_48Mhz(void);
@@ -58,8 +55,6 @@ void sb800_clk_output_48Mhz(void);
int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#else
void sb800_enable(struct device *dev);
-#endif
#endif /* SB800_H */