summaryrefslogtreecommitdiff
path: root/src/southbridge/amd
diff options
context:
space:
mode:
authorLi-Ta Lo <ollie@lanl.gov>2006-04-03 22:20:05 +0000
committerLi-Ta Lo <ollie@lanl.gov>2006-04-03 22:20:05 +0000
commit8854d30d6edb0e4e7f73cd2ab72b7cec78556846 (patch)
tree144a458964999f47883f1359c869f3dd2b3b2a34 /src/southbridge/amd
parent81efd7ab6deedf89af398d9039851d88db3aca0d (diff)
downloadcoreboot-8854d30d6edb0e4e7f73cd2ab72b7cec78556846.tar.xz
did I commit the last change?
try to fix 0x10000026 git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd')
-rw-r--r--src/southbridge/amd/cs5535/cs5535_early_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/cs5535/cs5535_early_setup.c b/src/southbridge/amd/cs5535/cs5535_early_setup.c
index a1cab08c88..e6b36435b2 100644
--- a/src/southbridge/amd/cs5535/cs5535_early_setup.c
+++ b/src/southbridge/amd/cs5535/cs5535_early_setup.c
@@ -97,7 +97,7 @@ static int cs5535_early_setup(void)
cs5535_setup_extmsr();
- msr = rdmsr(0x4c000014);
+ msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
print_debug("reboot from BIOS reset\n\r");