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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-31 19:22:16 +0200
committerMartin Roth <martinroth@google.com>2016-08-31 20:22:46 +0200
commitba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 (patch)
tree9f7e4416b63e26ee3f4df6f9a61ab55f377bcb5f /src/southbridge/broadcom/bcm5780/pcix.c
parent2e4d80687dd79890c7c9edad8dbaf6e89edf2afc (diff)
downloadcoreboot-ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1.tar.xz
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/broadcom/bcm5780/pcix.c')
-rw-r--r--src/southbridge/broadcom/bcm5780/pcix.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index 22dc771bab..8aa37a6757 100644
--- a/src/southbridge/broadcom/bcm5780/pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
@@ -22,22 +22,22 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ht_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0 ,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = 0 ,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};