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authorStefan Reinauer <stepan@coresystems.de>2010-01-16 17:53:38 +0000
committerStefan Reinauer <stepan@openbios.org>2010-01-16 17:53:38 +0000
commit9fe4d797a37671a65053add3f7cca27397db0b9b (patch)
tree5cabbdc8b6e7eb970891b55d1ea3727a4a71aca2 /src/southbridge/broadcom
parent984e0f3a0c3a82339ef8afcf7f315f377e0c81fc (diff)
downloadcoreboot-9fe4d797a37671a65053add3f7cca27397db0b9b.tar.xz
coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/broadcom')
-rw-r--r--src/southbridge/broadcom/bcm5785/bcm5785_sata.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
index 38cd6d4b3d..6818e6a2b0 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
@@ -52,13 +52,13 @@ static void sata_init(struct device *dev)
printk_debug("init PHY...\n");
for(i=0; i<4; i++) {
mmio = base + 0x100 * i;
- byte = readb(mmio + 0x40);
+ byte = read8(mmio + 0x40);
printk_debug("port %d PHY status = %02x\r\n", i, byte);
if(byte & 0x4) {// bit 2 is set
- byte = readb(mmio+0x48);
- writeb(byte | 1, mmio + 0x48);
- writeb(byte & (~1), mmio + 0x48);
- byte = readb(mmio + 0x40);
+ byte = read8(mmio+0x48);
+ write8(mmio + 0x48, byte | 1);
+ write8(mmio + 0x48, byte & (~1));
+ byte = read8(mmio + 0x40);
printk_debug("after reset port %d PHY status = %02x\r\n", i, byte);
}
}