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| author | Andrew Wu <arw@dmp.com.tw> | 2013-06-26 21:24:59 +0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-07-03 18:31:22 +0200 |
| commit | 00bf647bf6a980e8b9c3d8d91d79859c9b3de0a1 (patch) | |
| tree | 65109dd32c0d3d8dd0e8e7734cbdea7e93d12118 /src/southbridge/dmp/vortex86ex/southbridge.h | |
| parent | dd94fa93b403a73cc7d7b282eb6cefeb27512d13 (diff) | |
| download | coreboot-00bf647bf6a980e8b9c3d8d91d79859c9b3de0a1.tar.xz | |
Add support for DMP Vortex86EX PCI southbridge.
Change-Id: Iad11cb1b22e9d1e2953b12221541b1478cad9665
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/dmp/vortex86ex/southbridge.h')
| -rw-r--r-- | src/southbridge/dmp/vortex86ex/southbridge.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h new file mode 100644 index 0000000000..60e6dbcaac --- /dev/null +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_H +#define SOUTHBRIDGE_H + +#define SB PCI_DEV(0, 7, 0) +#define SB_REG_LPCCR 0x41 +#define SB_REG_FRCSCR 0x42 +#define SB_REG_PIRQ_X_ROUT 0x58 +#define SB_REG_UART_CFG_IO_BASE 0x60 +#define SB_REG_GPIO_CFG_IO_BASE 0x62 +#define SB_REG_CS_BASE0 0x90 +#define SB_REG_CS_BASE_MASK0 0x94 +#define SB_REG_CS_BASE1 0x98 +#define SB_REG_CS_BASE_MASK1 0x9c +#define SB_REG_IPPCR 0xb0 +#define SB_REG_PIRQ_X_ROUT2 0xb4 +#define SB_REG_OCDCR 0xbc +#define SB_REG_IPFCR 0xc0 +#define SB_REG_FRWPR 0xc4 +#define SB_REG_STRAP 0xce + +#define SYSTEM_CTL_PORT 0x92 + +#endif /* SOUTHBRIDGE_H */ |