diff options
| author | Andrew Wu <arw@dmp.com.tw> | 2013-07-09 21:29:25 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 23:51:29 +0200 |
| commit | 52914323bf876342ab3497bfc527f139680d1612 (patch) | |
| tree | ed83c710df72dc256c2cc99ec7efca9805d5e459 /src/southbridge/dmp/vortex86ex/southbridge.h | |
| parent | 8ee04d784cbaeb8a30276ac22aa99ddda44092b7 (diff) | |
| download | coreboot-52914323bf876342ab3497bfc527f139680d1612.tar.xz | |
Vortex86EX southbridge routes more built-in PCI device IRQs.
Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus.
Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/dmp/vortex86ex/southbridge.h')
| -rw-r--r-- | src/southbridge/dmp/vortex86ex/southbridge.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h index 60e6dbcaac..0cc28facb6 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.h +++ b/src/southbridge/dmp/vortex86ex/southbridge.h @@ -23,7 +23,7 @@ #define SB PCI_DEV(0, 7, 0) #define SB_REG_LPCCR 0x41 #define SB_REG_FRCSCR 0x42 -#define SB_REG_PIRQ_X_ROUT 0x58 +#define SB_REG_PIRQ_ROUTE 0x58 #define SB_REG_UART_CFG_IO_BASE 0x60 #define SB_REG_GPIO_CFG_IO_BASE 0x62 #define SB_REG_CS_BASE0 0x90 @@ -31,12 +31,15 @@ #define SB_REG_CS_BASE1 0x98 #define SB_REG_CS_BASE_MASK1 0x9c #define SB_REG_IPPCR 0xb0 -#define SB_REG_PIRQ_X_ROUT2 0xb4 +#define SB_REG_EXT_PIRQ_ROUTE 0xb4 #define SB_REG_OCDCR 0xbc #define SB_REG_IPFCR 0xc0 #define SB_REG_FRWPR 0xc4 #define SB_REG_STRAP 0xce +#define SB1 PCI_DEV(0, 7, 1) +#define SB1_REG_EXT_PIRQ_ROUTE2 0xb4 + #define SYSTEM_CTL_PORT 0x92 #endif /* SOUTHBRIDGE_H */ |