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| author | Andrew Wu <arw@dmp.com.tw> | 2013-10-31 20:12:09 +0800 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-22 14:57:09 +0100 |
| commit | fea5b50febb1d0cb37f8f77a44e5a0d6634c539d (patch) | |
| tree | c73b1a6b3f53d10a8111a6871dec5687fd84eccf /src/southbridge/dmp | |
| parent | 44af57a78bcb478f70f3047fcf950424f8e8e01c (diff) | |
| download | coreboot-fea5b50febb1d0cb37f8f77a44e5a0d6634c539d.tar.xz | |
vortex86ex: Change PCI S/B resource reservation functions for more I/O devices.
Originally, Vortex86EX PCI S/B internal resource reservation functions can
only support one big legacy I/O device space (0-0xfff).
Change function signature to support other non-legacy I/O device space in
the future.
Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3976
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/dmp')
| -rw-r--r-- | src/southbridge/dmp/vortex86ex/southbridge.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 61dceea124..5be857582b 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -505,21 +505,21 @@ static void fix_cmos_rtc_time(void) } } -static void vortex86_sb_set_io_resv(device_t dev, u32 io_resv_size) +static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size) { struct resource *res; - res = new_resource(dev, 1); - res->base = 0x0UL; - res->size = io_resv_size; + res = new_resource(dev, index); + res->base = base; + res->size = size; res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -static void vortex86_sb_set_spi_flash_size(device_t dev, u32 flash_size) +static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size) { /* SPI flash is in topmost of 4G memory space */ struct resource *res; - res = new_resource(dev, 2); + res = new_resource(dev, index); res->base = 0x100000000LL - flash_size; res->size = flash_size; res->limit = 0xffffffffUL; @@ -542,11 +542,11 @@ static void vortex86_sb_read_resources(device_t dev) flash_size = 64 * 1024 * 1024; } - /* Reserve space for I/O */ - vortex86_sb_set_io_resv(dev, 0x1000UL); + /* Reserve space for legacy I/O */ + vortex86_sb_set_io_resv(dev, 1, 0, 0x1000UL); /* Reserve space for flash */ - vortex86_sb_set_spi_flash_size(dev, flash_size); + vortex86_sb_set_spi_flash_size(dev, 2, flash_size); } static void southbridge_init_func1(struct device *dev) |