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| author | Tristan Corrick <tristan@corrick.kiwi> | 2018-11-30 22:53:50 +1300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-03 13:14:06 +0000 |
| commit | 63626b1a4a31588995ff6f0ba42952b6086cbded (patch) | |
| tree | 968555763c26df36af3e64b7322b3c68d6c19913 /src/southbridge/intel/bd82x6x/Makefile.inc | |
| parent | 32ceed8f269e48d9d500ee2ec9ba5b3f4435285e (diff) | |
| download | coreboot-63626b1a4a31588995ff6f0ba42952b6086cbded.tar.xz | |
sb/intel/common: Create a common PCH finalise implementation
The common finalise code is used by bd82x6x, Lynx Point, and Ibex Peak.
Lynx Point now benefits from being able to write-protect the flash chip.
For Lynx Point, writing the SPI OPMENU now happens in ramstage, as done
in bd82x6x.
Tested on an ASRock H81M-HDS (Lynx Point). When write-protection is
configured, flashrom reports all flash regions as read-only, and does
not manage to alter the contents of the flash chip.
Also tested on an ASUS P8H61-M LX (Cougar Point). Everything seems to
work as before.
Change-Id: I781082b1ed507b00815d1e85aec3e56ae5a4bef2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index c00b2c4263..24d7e2d24e 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -35,7 +35,7 @@ ramstage-y += watchdog.c ramstage-$(CONFIG_ELOG) += elog.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c romstage-y += early_spi.c early_pch_common.c |