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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-02-12 14:00:47 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-17 22:51:05 +0100 |
| commit | 645b376ec82c5343bd197f04fa9e7bb53ee23d69 (patch) | |
| tree | 6a6234b0a67f57ec240c093410d289f63a345fbc /src/southbridge/intel/bd82x6x/Makefile.inc | |
| parent | 8aa210bbf0343b1da1ab4e164c22da13c985a796 (diff) | |
| download | coreboot-645b376ec82c5343bd197f04fa9e7bb53ee23d69.tar.xz | |
Pantherpoint: Add XHCI device init
This enables power management and clock gating on XHCI.
Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 0b0385b46f..e921bc1d72 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -29,6 +29,7 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sata.c ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c ramstage-y += smbus.c |