diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2012-11-13 15:07:45 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2013-03-09 00:09:37 +0100 |
| commit | e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 (patch) | |
| tree | 34a5d2b6bb7bf08b82b5d1a8bf88c94294c704f7 /src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | |
| parent | 4733c647bc64cef86f03efd64a145e4da6fef123 (diff) | |
| download | coreboot-e7ae96f48834d57fd1a6c8940fa3f64b97520ed9.tar.xz | |
Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/globalnvs.asl')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 2fe092d952..99edc317cf 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -136,6 +136,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE + /* XHCI */ + Offset (0xb2), + XHCI, 8, /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address @@ -223,6 +226,17 @@ Method (S3GD) Store (Zero, \S33G) } +/* Set XHCI Mode enable */ +Method (XHCE) +{ + Store (One, \XHCI) +} + +/* Set XHCI Mode disable */ +Method (XHCD) +{ + Store (Zero, \XHCI) +} External (\_TZ.THRM) External (\_TZ.SKIN) |