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author | Martin Roth <martinroth@google.com> | 2018-05-06 21:06:18 -0500 |
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committer | Martin Roth <martinroth@google.com> | 2018-05-29 22:34:33 +0000 |
commit | a34b5bc6ed972dd1720345011b07e4a97b9e4594 (patch) | |
tree | 301d7695ae38047abc4c884692db892503342ecf /src/southbridge/intel/bd82x6x/acpi/pch.asl | |
parent | 14604dad4e470e8140d18296bd28b42c4bb26668 (diff) | |
download | coreboot-a34b5bc6ed972dd1720345011b07e4a97b9e4594.tar.xz |
southbridge/intel/bd82x6x: Remove unused argument from ACPI method
The method POSC was only using 2 of the 3 arguments passed in to it.
Remove the unused argument.
Change-Id: I6bbc2a034c79581fd338276eea56aac6d1affa58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/acpi/pch.asl')
-rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index cfa27d2b46..9f5033d759 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -254,10 +254,16 @@ Scope(\) Method (_OSC, 4) { + /* + * Arg0 - A Buffer containing a UUID + * Arg1 - An Integer containing a Revision ID of the buffer format + * Arg2 - An Integer containing a count of entries in Arg3 + * Arg3 - A Buffer containing a list of DWORD capabilities + */ /* Check for XHCI */ If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { - Return (^XHC.POSC(Arg1, Arg2, Arg3)) + Return (^XHC.POSC(Arg2, Arg3)) } /* Check for PCIe */ |