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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-10-26 10:12:15 +1100
committerNico Huber <nico.h@gmx.de>2014-11-05 14:41:47 +0100
commit9a817ef183177d4d9ce6fc37b26e00e147d29cd1 (patch)
treeac82e5076836ce20224b2e8babee9955138cf41e /src/southbridge/intel/bd82x6x/bootblock.c
parent169c0df6b8f07268e3bc49f35520df692705f5d8 (diff)
downloadcoreboot-9a817ef183177d4d9ce6fc37b26e00e147d29cd1.tar.xz
soutbridge/*/bootblock: Use pci_dev_t over device_t typedef
Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7193 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/bootblock.c')
-rw-r--r--src/southbridge/intel/bd82x6x/bootblock.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85a940e2de..b1b53af3ad 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
u8 reg8;
- device_t dev;
+ pci_devfn_t dev;
dev = PCI_DEV(0, 0x1f, 0);
@@ -50,7 +50,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void)
{
- device_t dev = PCI_DEV(0, 0x1f, 0);
+ pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
/* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);