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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-04 00:07:22 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-04 19:10:51 +0200 |
| commit | 8e073829ec69ee89b3e91f4c040c96988084a526 (patch) | |
| tree | 2e2b378ec66aa3ecd563b253726aae6e71db043a /src/southbridge/intel/bd82x6x/bootblock.c | |
| parent | cb91e1525eb0b81f9bc2e24e3404d6a9efc1cce3 (diff) | |
| download | coreboot-8e073829ec69ee89b3e91f4c040c96988084a526.tar.xz | |
Add support for Intel Panther Point PCH
Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/bootblock.c | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c new file mode 100644 index 0000000000..686e820e03 --- /dev/null +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "pch.h" + +static void store_initial_timestamp(void) +{ + /* On Cougar Point we have two 32bit scratchpad registers available: + * D0:F0 0xdc (SKPAD) + * D31:F2 0xd0 (SATA SP) + */ + tsc_t tsc = rdtsc(); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); +} + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(void) +{ + u8 reg8; + device_t dev; + + dev = PCI_DEV(0, 0x1f, 0); + + reg8 = pci_read_config8(dev, 0xdc); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, 0xdc, reg8); +} + +static void enable_port80_on_lpc(void) +{ + device_t dev = PCI_DEV(0, 0x1f, 0); + + /* Enable port 80 POST on LPC */ + pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); +#if 0 + RCBA32(GCS) &= (~0x04); +#else + volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); + u32 reg32 = *gcs; + reg32 = reg32 & ~0x04; + *gcs = reg32; + post_code(0x01); +#endif +} + +static void bootblock_southbridge_init(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + store_initial_timestamp(); +#endif + enable_spi_prefetch(); + enable_port80_on_lpc(); +} |