nb/intel/sandybridge: Move southbridge code to bd82x6x

Move the southbridge code to bd82x6x folder similar to the lynxpoint
implementation.

Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.

Change-Id: I8afc9f966033f45823f5dfde279e0f66de165e93
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 88436213a0..a50a159668 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -18,6 +18,9 @@
 #include <arch/cbfs.h>
 #include <ip_checksum.h>
 #include <device/pci_def.h>
+#include <southbridge/intel/common/gpio.h>
+#include <southbridge/intel/common/pmbase.h>
+
 /* For DMI bar.  */
 #include <northbridge/intel/sandybridge/sandybridge.h>
 
@@ -367,3 +370,34 @@ early_pch_init_native (void)
 
 	init_dmi();
 }
+
+static void pch_enable_bars(void)
+{
+	pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+	pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1);
+
+	pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80);
+
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+
+	/* Enable GPIO functionality. */
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+}
+
+static void pch_generic_setup(void)
+{
+	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
+	write_pmbase16(TCO1_CNT, 1 << 11);	/* halt timer */
+}
+
+void early_pch_init(void)
+{
+	pch_enable_lpc();
+
+	pch_enable_bars();
+
+	pch_generic_setup();
+
+	setup_pch_gpios(&mainboard_gpio_map);
+}