diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-07 00:54:42 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-08 15:28:06 +0000 |
| commit | 6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13 (patch) | |
| tree | 665b8f595d6940231e98a162709ea9dcf224920b /src/southbridge/intel/bd82x6x/early_rcba.c | |
| parent | d8abb266f45e573967f4375c289998fb844e90a4 (diff) | |
| download | coreboot-6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13.tar.xz | |
sb/intel/bd82x6x: Do cosmetic fixes
Make the code follow the coding style, and reflow things that fit in 96
characters.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_rcba.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_rcba.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 915a93599c..61877bb93d 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -5,8 +5,7 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include "pch.h" -void -southbridge_configure_default_intmap(void) +void southbridge_configure_default_intmap(void) { /* * For the PCH internal PCI functions, provide a reasonable @@ -83,8 +82,7 @@ southbridge_configure_default_intmap(void) (void) RCBA16(OIC); } -void -southbridge_rcba_config(void) +void southbridge_rcba_config(void) { RCBA32(FD) = PCH_DISABLE_ALWAYS; } |