diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-07 00:54:42 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-08 15:28:06 +0000 |
| commit | 6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13 (patch) | |
| tree | 665b8f595d6940231e98a162709ea9dcf224920b /src/southbridge/intel/bd82x6x/early_thermal.c | |
| parent | d8abb266f45e573967f4375c289998fb844e90a4 (diff) | |
| download | coreboot-6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13.tar.xz | |
sb/intel/bd82x6x: Do cosmetic fixes
Make the code follow the coding style, and reflow things that fit in 96
characters.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I6e0acdc9c21d4b416597dc776bd9abab12bff4a0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_thermal.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_thermal.c | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index ac7a3a4c90..e73f3a5908 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -36,34 +36,31 @@ void early_thermal_init(void) pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) | 5); + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); - write16p (0x40000004, 0x3a2b); - write8p (0x4000000c, 0xff); - write8p (0x4000000d, 0x00); - write8p (0x4000000e, 0x40); - write8p (0x40000082, 0x00); - write8p (0x40000001, 0xba); + write16p(0x40000004, 0x3a2b); + write8p(0x4000000c, 0xff); + write8p(0x4000000d, 0x00); + write8p(0x4000000e, 0x40); + write8p(0x40000082, 0x00); + write8p(0x40000001, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); - /* Northbridge temperature slope and offset. */ + /* Northbridge temperature slope and offset */ write16p(0x40000016, 0x808c); - write16p (0x40000014, 0xde87); + write16p(0x40000014, 0xde87); - /* Enable thermal data reporting, processor, PCH and northbridge. */ + /* Enable thermal data reporting, processor, PCH and northbridge */ write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); - /* Disable temporary BAR. */ - pci_write_config32(dev, 0x40, - pci_read_config32(dev, 0x40) & ~1); + /* Disable temporary BAR */ + pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_write_config32(dev, 0x40, 0); - write32 (DEFAULT_RCBA + 0x38b0, - (read32 (DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); + write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); } |