diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:53:59 +0300 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-06 20:42:52 +0100 |
commit | d45114ff59284cebc0c03821cc4d7782ca3bacf8 (patch) | |
tree | e7e02fdd04b60ce9735840780ae4bb734c3845f1 /src/southbridge/intel/bd82x6x/early_usb.c | |
parent | b1de92ee04c7a410cd50bd5d6e155d7343003fef (diff) | |
download | coreboot-d45114ff59284cebc0c03821cc4d7782ca3bacf8.tar.xz |
intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/early_usb.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index aa9b5fc88c..81d3b6b505 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -66,7 +66,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) for (i = 0; i < 22; i++) write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw (0x0000, DEFAULT_PMBASE | 0x003c); |