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| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-31 00:03:28 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-06-06 20:36:51 +0000 |
| commit | 1fc0edd9fe6b8072a87dce769789119e81af978b (patch) | |
| tree | d4e44ae76f4c7ff4acfe7e0d7909addcd8927d4d /src/southbridge/intel/bd82x6x/lpc.c | |
| parent | fa276862f2b98f480c2cd2d6948e332756a37d54 (diff) | |
| download | coreboot-1fc0edd9fe6b8072a87dce769789119e81af978b.tar.xz | |
src: Use pci_dev_ops_pci where applicable
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0f1d33e1c8..691db62cbe 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -861,10 +861,6 @@ void intel_southbridge_override_spi( memcpy(spi_config, &config->spi, sizeof(*spi_config)); } -static struct pci_operations pci_ops = { - .set_subsystem = pci_dev_set_subsystem, -}; - static struct device_operations device_ops = { .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, @@ -877,7 +873,7 @@ static struct device_operations device_ops = { .final = lpc_final, .enable = pch_lpc_enable, .scan_bus = scan_static_bus, - .ops_pci = &pci_ops, + .ops_pci = &pci_dev_ops_pci, }; |