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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-01 15:11:14 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-16 08:02:18 +0000 |
commit | b6585481e8cb30ed04a1673b170af3df9e0e4320 (patch) | |
tree | 09d4fad217ffb0dd6fb33b4d8e4c8dc20bfd708f /src/southbridge/intel/bd82x6x/lpc.c | |
parent | 94464474756f0cacdf04a70b95ec4a0462516a63 (diff) | |
download | coreboot-b6585481e8cb30ed04a1673b170af3df9e0e4320.tar.xz |
arch/x86: Create helper for APM_CNT SMI triggers
Attempts to write to APM_CNT IO port should always be guarded
with a test to verify SMI handler has been installed.
Immediate followup removes redundant HAVE_SMI_HANDLER tests.
Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 5e28cd2bc2..200463268f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -405,9 +405,7 @@ static void enable_clock_gating(struct device *dev) static void pch_set_acpi_mode(void) { if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); + apm_control(APM_CNT_ACPI_DISABLE); } } @@ -827,7 +825,7 @@ static void lpc_final(struct device *dev) if (CONFIG(HAVE_SMI_HANDLER)) { if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { - outb(APM_CNT_FINALIZE, APM_CNT); + apm_control(APM_CNT_FINALIZE); } } } |