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| author | Dan Elkouby <streetwalkermc@gmail.com> | 2018-04-01 19:54:57 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-07 16:04:07 +0000 |
| commit | 1a930584482c1cafb7ed02a9c37fcfe7cb61fb3f (patch) | |
| tree | 019efd266a74997017a5ceda8eb507a0b5cf2f3b /src/southbridge/intel/bd82x6x/lpc.c | |
| parent | 3ba380797b562bbeb7051abd4641bffcf1cf040c (diff) | |
| download | coreboot-1a930584482c1cafb7ed02a9c37fcfe7cb61fb3f.tar.xz | |
sb/intel/bd82x6x: Fix flashconsole after lockdown
SMM final locks the SPI BAR, which causes flashconsole to hang.
Re-init it like SMM does with CONFIG_SPI_FLASH_SMM.
Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/lpc.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e9e49649f2..f7bb7e4303 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -908,6 +908,12 @@ static void lpc_final(struct device *dev) if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); } } } |