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| author | Marc Jones <marc.jones@se-eng.com> | 2012-07-13 14:14:34 -0600 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:30:52 +0200 |
| commit | a0bec1745560492ec56d6149bcf3d3d0dcf3ccda (patch) | |
| tree | f9e72bcc82c7cfc3876afc2db4b64ae3dd5d6349 /src/southbridge/intel/bd82x6x/me.c | |
| parent | 1bb79bcf893d5abee14de4569e9230454116bfea (diff) | |
| download | coreboot-a0bec1745560492ec56d6149bcf3d3d0dcf3ccda.tar.xz | |
Reserve bd82x6x LPC decode ranges in the resource allocator
The LPC bus normally allocates the range for legacy devices,
0-0x1000. Some devices on LPC are above that range and need to
be accounted for. Check the decode range settings for addresses
> 0x1000 and reserve them.
Change-Id: Idba800d7cee3185296f29dd237ba306f3de8de55
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1337
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.c')
0 files changed, 0 insertions, 0 deletions