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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/bd82x6x/me.c
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
downloadcoreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.xz
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me.c')
-rw-r--r--src/southbridge/intel/bd82x6x/me.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 901e71dd5e..df188308cf 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -64,7 +64,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
-static u32 mei_base_address;
+static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
- u32 dword = read32(mei_base_address + offset);
+ u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
- write32(mei_base_address + offset, dword);
+ write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
- write32(mei_base_address + MEI_H_CB_WW, dword);
+ write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
- u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+ u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -501,11 +501,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
- mei_base_address =
- pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+ mei_base_address = (u32 *)
+ (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
- if (!mei_base_address || mei_base_address == 0xfffffff0)
+ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -627,7 +627,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
- mei_base_address = res->base;
+ mei_base_address = (u32*)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);