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authorJulius Werner <jwerner@chromium.org>2020-03-02 15:54:43 -0800
committerJulius Werner <jwerner@chromium.org>2020-05-09 00:21:59 +0000
commit29fbfcc472462e317e5dcf659523689f28bbfd98 (patch)
tree1034d9383bbdfdf8de648071213c18f019f861ce /src/southbridge/intel/bd82x6x/me_8.x.c
parent192a12fb6ab0b4a2033f087cec8a232d42a4c000 (diff)
downloadcoreboot-29fbfcc472462e317e5dcf659523689f28bbfd98.tar.xz
vboot: Clean up pre-RAM use of vboot_recovery_mode_enabled()
vboot_recovery_mode_enabled() was recently changed to assert() when it is called before vboot logic has run, because we cannot determine whether we're going to be in recovery mode at that point and we wanted to flush out existing uses that pretended that we could. Turns out there are a bunch of uses like that, and there is some code that is shared across configurations that can and those that can't. This patch cleans them up to either remove checks that cannot return true, or add explicit Kconfig guards to clarify that the code is shared. This means that using a separate recovery MRC cache is no longer supported on boards that use VBOOT_STARTS_IN_ROMSTAGE (this has already been broken with CB:38780, but with this patch those boards will boot again using their normal MRC caches rather than just die). Skipping the MRC cache and always regenerating from scratch in recovery mode is likewise no longer supported for VBOOT_STARTS_IN_ROMSTAGE. For FSP1.1 boards, none of them support VBOOT_STARTS_IN_BOOTBLOCK and that is unlikely to change in the future so we will just hardcode that fact in Kconfig (otherwise, fsp1.1 raminit would also have to be fixed to work around this issue). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I31bfc7663724fdacab9955224dcaf650d1ec1c3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me_8.x.c')
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index d240bf65d5..b529fe295f 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -403,38 +403,6 @@ static void __unused me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("Wireless LAN (WLAN)", cap->wlan);
}
-#if CONFIG(CHROMEOS) && 0 /* DISABLED */
-/* Tell ME to issue a global reset */
-static int mkhi_global_reset(void)
-{
- struct me_global_reset reset = {
- .request_origin = GLOBAL_RESET_BIOS_POST,
- .reset_type = CBM_RR_GLOBAL_RESET,
- };
- struct mkhi_header mkhi = {
- .group_id = MKHI_GROUP_ID_CBM,
- .command = MKHI_GLOBAL_RESET,
- };
- struct mei_header mei = {
- .is_complete = 1,
- .length = sizeof(mkhi) + sizeof(reset),
- .host_address = MEI_HOST_ADDRESS,
- .client_address = MEI_ADDRESS_MKHI,
- };
-
- /* Send request and wait for response */
- printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
- if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
- /* No response means reset will happen shortly... */
- halt();
- }
-
- /* If the ME responded it rejected the reset request */
- printk(BIOS_ERR, "ME: Global Reset failed\n");
- return -1;
-}
-#endif
-
/* Send END OF POST message to the ME */
static int __unused mkhi_end_of_post(void)
{
@@ -683,20 +651,6 @@ static void intel_me_init(struct device *dev)
if (intel_me_read_mbp(&mbp_data))
break;
-#if CONFIG(CHROMEOS) && 0 /* DISABLED */
- /*
- * Unlock ME in recovery mode.
- */
- if (vboot_recovery_mode_enabled()) {
- /* Unlock ME flash region */
- mkhi_hmrfpo_enable();
-
- /* Issue global reset */
- mkhi_global_reset();
- return;
- }
-#endif
-
if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) {
me_print_fw_version(&mbp_data.fw_version_name);
me_print_fwcaps(&mbp_data.fw_caps_sku);