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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 22:09:01 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-10 18:48:32 +0000 |
| commit | c803f65206188ca74526054c54bce4f405a55850 (patch) | |
| tree | 9ce8dd5df1ac5e56912bb0f72c19274bfcfd0acb /src/southbridge/intel/bd82x6x/me_8.x.c | |
| parent | 7333ea91eae33a874cf5187bc04906f6d2f1e3bf (diff) | |
| download | coreboot-c803f65206188ca74526054c54bce4f405a55850.tar.xz | |
sb/intel/bd82x6x: Use PCI bitwise ops
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me_8.x.c')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index dd972d2b4e..e65b8e5026 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -432,7 +432,6 @@ void intel_me8_finalize_smm(void) { struct me_hfs hfs; u32 reg32; - u16 reg16; mei_base_address = (void *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -455,10 +454,8 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); - reg16 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); + pci_and_config16(PCH_ME_DEV, PCI_COMMAND, + ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); |