diff options
author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/southbridge/intel/bd82x6x/me_8.x.c | |
parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/bd82x6x/me_8.x.c')
-rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index bdd57cdd33..a6ffe896c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -62,7 +62,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) +#if CONFIG(DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -423,7 +423,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -575,7 +575,7 @@ static me_bios_path intel_me_path(struct device *dev) path = ME_ERROR_BIOS_PATH; } -#if IS_ENABLED(CONFIG_ELOG) +#if CONFIG(ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -664,7 +664,7 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if IS_ENABLED(CONFIG_CHROMEOS) +#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -705,7 +705,7 @@ static void intel_me_init(struct device *dev) if (intel_me_read_mbp(&mbp_data)) break; -#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ +#if CONFIG(CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ |